MT90222

The MT90222/223/224 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/223/224 architecture, up to 16 physical and independent serial links can be terminated through the utilization of off-the-shelf, traditional T1/E1/J1 framers/LIUs and DSL chip sets. The MT90222/223/224 device can also provide up to 10 Mb/s per link data rates for unframed serial TDM transmissions for xDSL applications.

The MT90222/223/224 device provides ATM system designers with a flexible architecture when implementing ATM access over existing trunk interfaces, allowing a migration towards ATM service technology. In addition to the design of ATM UNI specifications for T1/E1 rates, the MT90222/223/224 device is compliant with the ATM FORUM IMA specifications for controlling IMA groups of up to 16 trunks in a single chip. The MT90222/223/224 can be configured to operate in different modes to facilitate the implementation of the IMA function at both CPE and Central Office sites. For systems targeting ATM over T1/E1 with IMA and TC operating simultaneously, the MT90222/223/224 device provides the ideal architecture and capabilities.

The MT90222 provides up to 8 internal IMA processors and allows for bandwidth scaleability through the use of the UTOPIA MPHY, Level 1 and Level 2 specification at rates up to 52 Mhz.