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PC7457, PC74572-1, PC745B

Table of contents:
Info of PC7457
Info of PC74572-1
Info of PC745B

PC7457, PC74572-1, PC745B Selling Leads, Datasheet

MFG:Atmel Package Cooled:N/A D/C:09+

PC7457, PC74572-1, PC745B Datasheet download

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Part Number: PC7457

MFG: Atmel

Package Cooled: N/A

D/C: 09+

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PC7457 Parameters

PC7457 Datasheet and Application Notes

PC7457-RISC Microprocessor Preliminary

PC7457 General Description

32-bit RISC Microprocessor, 1000 MHz

PC7457 Maximum Ratings

Symbol	Characteristic		Maximum Value	Unit
V_DD⁽²⁾	Core supply voltage		-0.3 to 1.60	V
AV_DD⁽²⁾	PLL supply voltage		-0.3 to 1.60	V
OV_DD⁽³⁾⁽⁴⁾	Processor bus supply voltage	BVSEL = 0	-0.3 to 1.95	V
OV_DD⁽³⁾⁽⁵⁾	Processor bus supply voltage	BVSEL = HRESET or OV_DD	-0.3 to 2.7	V
GV_DD⁽³⁾⁽⁶⁾	L3 bus supply voltage	L3VSEL = ¬HRESET	-0.3 to 1.65	V
GV_DD⁽³⁾⁽⁷⁾		L3VSEL = 0	-0.3 to 1.95	V
GV_DD⁽³⁾⁽⁸⁾		L3VSEL = HRESET or GV_DD	-0.3 to 2.7	V
V_IN^(9)(10)	Input voltage	Processor bus	-0.3 to OV_DD+ 0.3	V
V_IN^(9)(10)		L3 bus	-0.3 to GV_DD + 0.3	V
V_IN		JTAG signals	-0.3 to OV_DD + 0.3	V
T_STG	Storage temperature range		-55 to 150	°C

Notes:
1. Functional and tested operating conditions are given in Table 3 on page 12. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
2. Caution: VDD/AVDD must not exceed OVDD/GVDD by more than 1V during normal operation; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
3. Caution: OVDD/GVDD must not exceed VDD/AVDD by more than 2V during normal operation; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
4. BVSEL must be set to 0, such that the bus is in 1.8V mode.
5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5V mode.
6. L3VSEL must be set to ¬HRESET (inverse of HRESET ), such that the bus is in 1.5V mode.

PC7457 Typical Application

PC7457-RISC Microprocessor Preliminary

PC745B General Description

The PC755B and PC745B PowerPC^® microprocessors are high-performance, lowpower, 32-bit implementations of the PowerPC Reduced Instruction Set Computer (RISC) architecture, especially enhanced for embedded applications.

The PC755B and PC745B microprocessors differ only in that the PC755B features an enhanced, dedicated L2 cache interface with on-chip L2 tags. The PC755B is a dropin replacement for the award winning PowerPC 750™microprocessor and is footprint and user software code compatible with the MPC7400 microprocessor with AltiVec™ technology. The PC745B is a drop-in replacement for the PowerPC 740™ microprocessor and is also footprint and user software code compatible with the PowerPC 603e™ microprocessor. PC755B/745B microprocessors provide on-chip debug support and are fully JTAG-compliant.

The PC745B microprocessor is pin compatible with the TSPC603e family.

PC745B Maximum Ratings

Characteristic		Symbol	Maximum Value	Unit
Core supply voltage⁽⁴⁾		V_DD	-0.3 to 2.5	V
PLL supply voltage⁽⁴⁾		AV_DD	-0.3 to 2.5	V
L2 DLL supply voltage⁽⁴⁾		L2AV_DD	-0.3 to 2.5	V
Processor bus supply voltage⁽³⁾		OV_DD	-0.3 to 3.6	V
L2 bus supply voltage⁽³⁾		L2OV_DD	-0.3 to 3.6	V
Input voltage	Processor bus⁽²⁾⁽⁵⁾	V_in	-0.3 to OV_DD + 0.3V	V
	L2 Bus⁽²⁾⁽⁵⁾	V_in	-0.3 to L2OV_DD + 0.3V	V
	JTAG Signals	V_in	-0.3 to 3.6	V
Storage temperature range		T_stg	-55 to 150	°C

Notes: 1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
2. Caution: VIN must not exceed OV_DD or L2OV_DD by more than 0.3V at any time including during power-on reset.
3. Caution: L2OV_DD/OV_DD must not exceed V_DD/AV_DD/L2AV_DD by more than 1.6V during normal operation; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
4. Caution: V_DD/AV_DD/L2AV_DDmust not exceed L2OV_DD/OV_DD by more than 0.4V during normal operation; this limit may beexceeded for a maximum of 20 ms during power-on reset and power-down sequences.
5. VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

PC745B Features

18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz (PC755B)
15.7SPECint95, 9SPECfp95 at 350 MHz (PC745B)
733 MIPS at 400 MHz (PC755B) at 641 MIPS at 350 MHz (PC745B)
Selectable Bus Clock (12 CPU Bus Dividers up to 10x)
PD Typical 6.4W at 400 MHz, Full Operating Conditions.
Nap, Doze and Sleep Modes for Power Savings
Superscalar (3 Instructions per Clock Cycle) Two Instruction + Branch
4 Beta Byte Virtual Memory, 4-GByte of Physical Memory
64-bit Data and 32-bit Address Bus Interface
32-KB Instruction and Data Cache
Six Independent Execution Units
Write-back and Write-through Operations
f_INTmax = 400 MHz (TBC)
f_BUS max = 100 MHz
Voltage I/O 2.5V/3.3V; Voltage Int 2.0V

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