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PCI2040GGU, PCI2040PGE, PCI2050

Table of contents:
Info of PCI2040GGU
Info of PCI2040PGE
Info of PCI2050

PCI2040GGU, PCI2040PGE, PCI2050 Selling Leads, Datasheet

MFG:Texas Instruments Category:Integrated Circuits (ICs) Package Cooled:BGA?(GGU) | 144 D/C:04+

PCI2040GGU, PCI2040PGE, PCI2050 Datasheet download

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Part Number: PCI2040PGE

Category: Integrated Circuits (ICs)

MFG: Texas Instruments

Package Cooled: BGA?(GGU) | 144

D/C: 04+

Description: IC PCI-DSP BRIDGE CNTRLR 144LQFP

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PCI2040GGU Parameters

Technical/Catalog Information	PCI2040GGU
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Controller Type	PC Card Controller
Interface	PCI
Voltage - Supply	3 V ~ 3.6 V
Current - Supply	-
Package / Case	144-BGA MICROSTAR
Packaging	Tube
Operating Temperature	0°C ~ 70°C
Drawing Number	296; 4073221-2; GGU; 144
Lead Free Status	Contains Lead
RoHS Status	RoHS Non-Compliant
Other Names	PCI2040GGU PCI2040GGU 296 9633 5 ND 29696335ND 296-9633-5

PCI2040PGE Parameters

Technical/Catalog Information	PCI2040PGE
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Controller Type	PC Card Controller
Interface	PCI
Voltage - Supply	3 V ~ 3.6 V
Current - Supply	-
Package / Case	144-LQFP
Packaging	Tray
Operating Temperature	0°C ~ 70°C
Drawing Number	296; 4040147; PGE; 144
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	PCI2040PGE PCI2040PGE 296 9634 ND 2969634ND 296-9634

PCI2050 General Description

The Texas Instruments PCI2050 PCI-to-PCI bridge provides a high performance connection path between two peripheral component interconnect (PCI) buses. Transactions occur between masters on one PCI bus and targets on another PCI bus, and the PCI2050 allows bridged transactions to occur concurrently on both buses. The bridge supports burst-mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently.

The PCI2050 bridge is compliant with the PCI Local Bus Specification, and can be used to overcome the electrical loading limits of 10 devices per PCI bus and one PCI device per expansion slot by creating hierarchical buses. The PCI2050 provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with an external secondary PCI bus arbiter.

The compact-PCI hot-swap extended PCI capability is provided which makes the PCI2050 an ideal solution for multifunction compact PCI cards and adapting single function cards to hot-swap compliance.

The PCI2050 bridge is compliant with the PCI-to-PCI Bridge Specification 1.1. The PCI 2050 provides compliance for PCI Power Management 1.0 and 1.1. The PCI2050 has been designed to lead the industry in power conservation. An advanced CMOS process is used to achieve low system power consumption while operating at PCI clock rates up to 33 MHz.

PCI2050 Maximum Ratings

Supply voltage range: V_CC . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V
                                  : S_V_CCP . . . . . . . . . . . . . . . . . .          0.5 V to 6 V
                                  : P_V_CCP. . . . . . . . . . . . . . . . . . .        0.5 V to 6 V
Input voltage range, V_I: P_CI . . . . . . . . . . . . . . . . . . . . . .     0.5 V to 6.5 V
Output voltage range, V_O: P_CI . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, I_IK (V_I< 0 or V_I> V_CC) (see Note 1) . . . . . . . ±20 mA
Output clamp current, I_OK (V_O < 0 or V_O> V_CC) (see Note 2) . . . . . ±20 mA
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . .65°C to 150°C
Virtual junction temperature, T_J . . . . . . . . . . . . . . . . . . . . . . . . . . .     150°C

PCI2050 Features

• Configurable for PCI Bus Power Management Interface Specification
• Provides compact PCI hot-swap functionality
• 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
• Two 32-bit, 33-MHz PCI buses
• Provides internal two-tier arbitration for up to nine secondary bus masters and supports an external secondary bus arbiter
• Burst data transfers with pipeline architecture to maximize data throughput in both directions
• Independent read and write buffers for each direction
• Up to three delayed transactions in both directions
• Provides 10 secondary PCI clock outputs
• Predictable latency per PCI Local Bus Specification
• Propagates bus locking
• Secondary bus is driven low during reset
• Provides VGA/palette memory and I/O, and subtractive decoding options
• Advanced submicron, low-power CMOS technology
• Packaged in 208-terminal QFP or 209-terminal MicroStar BGA

PCI2050 Connection Diagram

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