PCI 6150

Features:

• PCI Local Bus Specification Rev 2.3 support
• High speed PCI buffer supports 3.3V
signaling with 5V input signal tolerance
• Asynchronous design supports standard
66Mhz to 33MHz and faster secondary port
speed such as 33Mhz to 40/50/60/66MHz conversion
• Programmable Address Translation to Secondary Bus
• Flow-Through 0 wait state burst up to 4K
bytes for optimal large volume data transfer
• Supports up to 4 simultaneous posted write
transactions and 4 simultaneous Delayed
transactions in each direction
• Provides 1K Bytes of buffering
256 byte upstream posted write buffer
256 byte downstream posted write buffer
256 byte upstream read data buffer
256 byte downstream read data buffer
• Programmable prefectch amount of up to
256 bytes for maximum read performance optimization
• Supports out of order delayed transactions
• CPCI Hot Swap Specification PICMG 2.1
R2.0 with PI = 1 support
• Device Hiding support eliminates midtransaction
extraction problems
• Serial EEPROM loadable and
programmable PCI READ ONLY Register
configurations.
• External arbiter or programmable arbitration
for 9 bus masters on secondary interface support
• 10 Secondary clock outputs with pin
controlled enable and individual maskable
control
• Power Management D3 Cold Wakeup capable
• 4 GPIO pins with output control
• Enhanced address decoding
Support 32-bit I/O address range
32-bit memory-mapped I/O address range
ISA aware mode for legacy support in
the first 64KB of I/O address range
VGA addressing and palette snooping support
• Provides an IEEE standard 1149.1 JTAG
interface for boundary scan test
• PCI 6150 uses Industry standard 208 pin PQFP package




Pinout






Specifications

Parameter	Minimum	Maximum
Storage Temperature Range	-55 °C	125 °C
Junction Temperature		125 °C
Supply Voltage, VDD		3.9V
Maximum Voltage to signal pins		5.5V
Maximum Power		1.8W

Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

Description

32-bit; 33MHz PCI-to-PCI Bridge, 17 x 17mm BGA or 31 x 31mm PQFPThe FastLane™ PCI 6150 PCI-to-PCI Bridge (HB4) is designed for high performance, high availability applications in hot swap, bus expansions, programmable data transfer rate control, frequency conversions from slower PCI to faster PCI or from faster PCI to slower PCI buses. The PCI 6150 has sophisticated buffer management and buffer configuration options designed to provide customizable performance optimization. The PCI 6150 is offered in a 17 x 17mm 256-ball BGA or 31 x 31mm 208-pin PQFP. This device is available in leaded and lead-free packaging.