PM5344-R1/PV689101B, PM5345, PM5345-160 Selling Leads, Datasheet
MFG:PMC Package Cooled:QFP160 D/C:08+
PM5344-R1/PV689101B, PM5345, PM5345-160 Datasheet download

Part Number: PM5344-R1/PV689101B
MFG: PMC
Package Cooled: QFP160
D/C: 08+
MFG:PMC Package Cooled:QFP160 D/C:08+
PM5344-R1/PV689101B, PM5345, PM5345-160 Datasheet download

MFG: PMC
Package Cooled: QFP160
D/C: 08+
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Datasheet: PM501
File Size: 313656 KB
Manufacturer:
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PDF/DataSheet Download
Datasheet: PM5345
File Size: 632440 KB
Manufacturer: PMC [PMC-Sierra, Inc]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: PM501
File Size: 313656 KB
Manufacturer:
Download : Click here to Download
The PM5345 S/UNI SATURN User Network Interface is a monolithic integrated circuit that implements the SONET/SDH processing and ATM mapping functions of a 155 Mbit/s ATM User-Network Interface.
The S/UNI receives SONET/SDH frames, via a bit serial or byte serial interface, and processes section, line, and path overhead. It performs framing (A1, A2), descrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. Line and path far end block error indications (Z2, G1) are also accumulated. The S/UNI interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope which carries the received ATM cell payload. In addition to its basic processing of the received SONET/SDH overhead, the S/UNI provides convenient access to all overhead bytes, which are extracted and serialized on lower rate interfaces, allowing additional external processing of overhead.
The S/UNI frames to the ATM payload using cell delineation. HCS error correction is provided. Idle/unassigned cells may be dropped according to a programmable filter. Cells are also dropped upon detection of an uncorrectable header check sequence error. The ATM cell payloads are descrambled. The ATM cells that are passed are written to a four cell FIFO buffer. The received cells are read from the FIFO using a generic 9 bit wide or 17 bit wide datapath interface. Counts of received ATM cell headers that are errored and uncorrectable and also those that are errored and correctable are accumulated independently for performance monitoring purposes.
The S/UNI transmits SONET/SDH frames, via a bit serial or a byte serial interface, and formats section, line, and path overhead appropriately. It performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity (B1, B2, B3) as required to allow performance monitoring at the far end. Line and path far end block error indications (Z2, G1) are also inserted. The S/UNI generates the payload pointer (H1, H2) and inserts the synchronous payload envelope which carries the ATM cell payload. In addition to its basic formatting of the transmitted SONET/SDH overhead, the S/UNI provides convenient access to all overhead bytes, which are optionally inserted from lower rate serial interfaces, allowing external sourcing of overhead. The S/UNI also supports the insertion of a large variety of errors into the transmit stream, such as framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for system diagnostics and tester applications.
| Parameter | Value |
| Ambient Temperature under Bias | -40°C to +70°C |
| Storage Temperature | -40°C to +125°C |
| Supply Voltage | -0.5V to +6.0V |
| Voltage on Any Pin | -0.5V to VDD+0.5V |
| Static Discharge Voltage | ±500 V |
| Latch-Up Current | ±100 mA |
| DC Input Current | ±20 mA |
| Lead Temperature | +230°C |
| Absolute Maximum Junction Temperature |
+150°C |
| Power Dissipation | 1.5 W |
· Monolithic Saturn Network Interface that implements the ATM physical layer for Broadband ISDN according to the ATM Forum User Network Interface Specification and CCITT Recommendation I.432.
· Operates at 155.52 MHz in conjunction with an external clock and data recovery device. Provides on-chip parallel to serial and serial to parallel circuits with pseudo ECL interfaces to process a duplex 155.52 Mbit/s STS- 3c/STM-1 data stream.
· Supports a 19.44 Mbyte/s line interface option for devices requiring a byteserial STS-3c/STM-1 interface.
· Provides 4 cell deep FIFO buffers in both transmit and receive paths with a byte-wide or word-wide system side datapath interface.
· Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.
· Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
· Low power, +5 Volt, CMOS technology.
· 160 pin high performance plastic quad flat pack (PQFP) package.

