PM5345RI, PM5345-RI, PM5346 Selling Leads, Datasheet
MFG:PMC Package Cooled:QFP D/C:05-07+
PM5345RI, PM5345-RI, PM5346 Datasheet download
Part Number: PM5345RI
MFG: PMC
Package Cooled: QFP
D/C: 05-07+
PM5345RI, PM5345-RI, PM5346
- Table of contents:
Info of PM5345RI
Info of PM5345-RI
Info of PM5346
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About PM501
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Datasheet: PM501
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About PM501
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Datasheet: PM501
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About PM5346
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Datasheet: PM5346
File Size: 549259 KB
Manufacturer: PMC [PMC-Sierra, Inc]
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PM5346 General Description
The PM5346 S/UNI-LITE Saturn User Network Interface is a monolithic integrated circuit that implements the SONET/SDH processing and ATM mapping functions of a 155 Mbit/s or 51Mbit/s ATM User Network Interface. It is fully compliant with both SONET and SDH requirements and ATM Forum UNI specifications.
The S/UNI-LITE receives SONET/SDH frames via a bit serial interface, recovers clock and data, and processes section, line, and path overhead. It performs framing (A1, A2), descrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. Line and path far end block error indications (Z2, G1) are also accumulated. The S/UNI-LITE interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope which carries the received ATM cell payload.
The S/UNI-LITE frames to the ATM payload using cell delineation. HCS error correction is provided. Idle/unassigned cells may be dropped according to a programmable filter. Cells are also dropped upon detection of an uncorrectable header check sequence error. The ATM cell payloads are descrambled. Generic flow control (GFC) bits from error free cells are extracted and presented on a serial link for external processing.
Legitimate ATM cells are written to a four cell FIFO buffer. These cells are read from the FIFO using a synchronous 8 bit wide datapath interface with cell-based handshake. Counts of received ATM cell headers that are errored and uncorrectable, those that are errored and correctable and all passed cells are accumulated independently for performance monitoring purposes.
The S/UNI-LITE transmits SONET/SDH frames via a bit serial interface and formats section, line, and path overhead appropriately. It performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity (B1, B2, B3) as required to allow performance monitoring at the far end. Line and path far end block error indications (Z2, G1) are also inserted.
The S/UNI-LITE generates the payload pointer (H1, H2) and inserts the synchronous payload envelope which carries the ATM cell payload. It supports the insertion of a variety of errors into the transmit stream, such as framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for system diagnostics.
ATM cells are written to an internal programmable-length 4-cell FIFO using a synchronous 8 bit wide datapath interface. Idle/unassigned cells are automatically inserted when the internal FIFO contains less than one cell or the XOFF input is asserted. Generic flow control (GFC) bits may be inserted downstream of the FIFO via a serial link so that all FIFO latency may be bypassed. A Transmission Off (XOFF) input is provided to allow the suspension of active ATM cell transmission independent of the FIFO fill state.
The S/UNI-LITE generates of the header check sequence and scrambles the payload of the ATM cells. Payload scrambling can be disabled. No line rate clocks are required directly by the S/UNI-LITE as it synthesizes the transmit clock and recovers the receive clock using a 19.44 MHz or 6.48 MHz reference clock.
The S/UNI-LITE is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. It is implemented in low power, +5 Volt CMOS technology. It has TTL and pseudo ECL (PECL) compatible inputs and TTL compatible outputs and is packaged in a 128 pin PQFP package.
PM5346 Maximum Ratings
Ambient Temperature under Bias . . . . . .0°C to +70°C
Storage Temperature . . . . . . . . . . . .-40°C to +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . -0.5V to +6.0V
Voltage on Any Pin . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Static Discharge Voltage . . . . . . . . . . . . . . . . . ..±500 V
Latch-Up Current . . . . . . . . . . . . . . . . . . . . . . .±100 mA
DC Input Current . . . . . . . . . . . . . . . . . . . . . . . .±20 mA
Lead Temperature . . . . . . . . . . . . . . . . . . . . . . +300°C
Absolute Maximum Junction Temperature . . . . .+150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . ..1 W
Storage Temperature . . . . . . . . . . . .-40°C to +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . -0.5V to +6.0V
Voltage on Any Pin . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Static Discharge Voltage . . . . . . . . . . . . . . . . . ..±500 V
Latch-Up Current . . . . . . . . . . . . . . . . . . . . . . .±100 mA
DC Input Current . . . . . . . . . . . . . . . . . . . . . . . .±20 mA
Lead Temperature . . . . . . . . . . . . . . . . . . . . . . +300°C
Absolute Maximum Junction Temperature . . . . .+150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . ..1 W
PM5346 Features
• Single chip ATM User-Network Interface operating at 155.52 and 51.84 Mbit/s. Also capable of operating at ATM Forum mid-range PHY subrates of 25.92 and 12.96 Mbit/s.
• Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432.
• Processes duplex 155.52 Mbit/s STS-3c/STM-1 or 51.84 Mbit/s STS-1 data streams with on-chip clock and data recovery and clock synthesis.
• Provides Saturn Compliant Interface - PHYsical layer (SCI-PHY™) FIFO buffers in both transmit and receive paths with parity support.
• Inserts and extracts the generic flow control (GFC) bits via a simple serial interface and provides a transmit XOFF function to allow for local flow control.
• Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.
• Low power, +5 Volt, CMOS technology.
• 128 pin high performance plastic quad flat pack (PQFP) 14 mm x 20 mm package.
The receiver section:
• Provides a serial interface at 155.52 or 51.84 Mbit/s
• Recovers the clock and data; frames to the recovered data stream; descrambles the received data; interprets the received payload pointer (H1, H2); and extracts the STS-3c or STS-1 synchronous payload envelope (VC4) and path overhead.
• Extracts ATM cells from the synchronous payload envelope using ATM cell delineation and provides optional ATM cell payload descrambling, header check sequence (HCS) error detection and error correction, and idle/unassigned cell filtering.
• Provides a synchronous 8-bit wide, four cell FIFO buffer.
• Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line alarm indication signal (AIS), line remote defect indication (RDI), loss of pointer (LOP), path alarm indication signal (AIS), loss of cell delineation and path RDI.
• Counts received section BIP-8 (B1) errors, received line BIP-8/24 (B2) errors, line far end block errors (FEBE), received path BIP-8 (B3) errors and path far end block errors (FEBE).
• Counts received HCS errored cells that are discarded, received HCS errored cells that are corrected and passed on, and the total received cells passed on.
The transmitter section:
• Provides a synchronous 8-bit wide, four cell FIFO buffer.
• Provides idle/unassigned cell insertion, HCS generation/insertion, and ATM cell payload scrambling; Inserts ATM cells into the transmitted STS-3c (STM-1) or STS-1 synchronous payload envelope using H4 framing
• Generates the transmit payload pointer (H1, H2) and inserts the path overhead; scrambles the transmitted STS-3c (STM-1) or STS-1 stream and inserts framing bytes (A1, A2) and the identity byte (C1).
• Synthesizes the 155.52 MHz, 51.84 MHz transmit clock from a one-eighth frequency reference.
• Provides a serial interface at 155.52 or 51.84 Mbit/s
• Inserts path alarm indication signal (AIS), path remote defect indication (RDI), line alarm indication signal (AIS) and line RDI.
• Inserts path BIP-8 codes (B3), path far end block error (FEBE) indications, line BIP-8/24 codes (B2), line far end block error (FEBE) indications, section BIP-8 codes (B1) to allow performance monitoring at the far end.
• Allows forced insertion of all zeros data (after scrambling) or corruption of framing byte or section, line, or path BIP-8 codes for diagnostic purposes.
• Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432.
• Processes duplex 155.52 Mbit/s STS-3c/STM-1 or 51.84 Mbit/s STS-1 data streams with on-chip clock and data recovery and clock synthesis.
• Provides Saturn Compliant Interface - PHYsical layer (SCI-PHY™) FIFO buffers in both transmit and receive paths with parity support.
• Inserts and extracts the generic flow control (GFC) bits via a simple serial interface and provides a transmit XOFF function to allow for local flow control.
• Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.
• Low power, +5 Volt, CMOS technology.
• 128 pin high performance plastic quad flat pack (PQFP) 14 mm x 20 mm package.
The receiver section:
• Provides a serial interface at 155.52 or 51.84 Mbit/s
• Recovers the clock and data; frames to the recovered data stream; descrambles the received data; interprets the received payload pointer (H1, H2); and extracts the STS-3c or STS-1 synchronous payload envelope (VC4) and path overhead.
• Extracts ATM cells from the synchronous payload envelope using ATM cell delineation and provides optional ATM cell payload descrambling, header check sequence (HCS) error detection and error correction, and idle/unassigned cell filtering.
• Provides a synchronous 8-bit wide, four cell FIFO buffer.
• Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line alarm indication signal (AIS), line remote defect indication (RDI), loss of pointer (LOP), path alarm indication signal (AIS), loss of cell delineation and path RDI.
• Counts received section BIP-8 (B1) errors, received line BIP-8/24 (B2) errors, line far end block errors (FEBE), received path BIP-8 (B3) errors and path far end block errors (FEBE).
• Counts received HCS errored cells that are discarded, received HCS errored cells that are corrected and passed on, and the total received cells passed on.
The transmitter section:
• Provides a synchronous 8-bit wide, four cell FIFO buffer.
• Provides idle/unassigned cell insertion, HCS generation/insertion, and ATM cell payload scrambling; Inserts ATM cells into the transmitted STS-3c (STM-1) or STS-1 synchronous payload envelope using H4 framing
• Generates the transmit payload pointer (H1, H2) and inserts the path overhead; scrambles the transmitted STS-3c (STM-1) or STS-1 stream and inserts framing bytes (A1, A2) and the identity byte (C1).
• Synthesizes the 155.52 MHz, 51.84 MHz transmit clock from a one-eighth frequency reference.
• Provides a serial interface at 155.52 or 51.84 Mbit/s
• Inserts path alarm indication signal (AIS), path remote defect indication (RDI), line alarm indication signal (AIS) and line RDI.
• Inserts path BIP-8 codes (B3), path far end block error (FEBE) indications, line BIP-8/24 codes (B2), line far end block error (FEBE) indications, section BIP-8 codes (B1) to allow performance monitoring at the far end.
• Allows forced insertion of all zeros data (after scrambling) or corruption of framing byte or section, line, or path BIP-8 codes for diagnostic purposes.
PM5346 Typical Application
• Workstations and Personal Computers
• Switches and Hubs
• Routers
• SONET or SDH ATM Interfaces
• 155 and 51 Mbit/s UTP-5 ATM LANs
• 51, 25 and 13 Mbit/s UTP-3 ATM LANs
• Switches and Hubs
• Routers
• SONET or SDH ATM Interfaces
• 155 and 51 Mbit/s UTP-5 ATM LANs
• 51, 25 and 13 Mbit/s UTP-3 ATM LANs
PM5346 Connection Diagram
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