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PPC440EP, PPC440EP-3JB533C, PPC440GP-3CC333C

Table of contents:
Info of PPC440EP
Info of PPC440EP-3JB533C
Info of PPC440GP-3CC333C

PPC440EP, PPC440EP-3JB533C, PPC440GP-3CC333C Selling Leads, Datasheet

MFG:3266 Package Cooled:BGA D/C:N/A

PPC440EP, PPC440EP-3JB533C, PPC440GP-3CC333C Picture

PPC440EP, PPC440EP-3JB533C, PPC440GP-3CC333C Datasheet download

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Part Number: PPC440EP

MFG: 3266

Package Cooled: BGA

D/C: N/A

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PPC440EP General Description

Designed specifically to address high-end embedded applications, the PowerPC 440EP (PPC440EP) provides a high-performance, low- power solution that interfaces to a wide range of peripherals and incorporates on-chip power management features.

This chip contains a high-performance RISC processor, a floating point unit, DDR SDRAM controller, PCI bus interface, control for external ROM and peripherals, DMA with scatter-gather support, Ethernet ports, serial ports, IIC interfaces, SPI interface, USB ports, NAND Flash interface, and general purpose I/O.

Technology: CMOS Cu-11, 0.13m.

Package: 35mm, 456-ball standard plastic ball grid array (E-PBGA), with and without lead (RoHS compliant).

Typical power (measured): Less than 3W at 533MHz, 2.5W at 400MHz.

Supply voltages required: 3.3V, 2.5V, 1.5V.

PPC440EP Maximum Ratings

The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device. None of the performance specification contained in this document are guaranteed when operating at these maximum ratings.

Characteristic	Symbol	Value	Unit	Notes
Supply Voltage (Internal Logic)	V_DD	0 to +1.65	V	1
Supply Voltage (I/O, except SDRAM, Ethernet)	OV_DD	0 to +3.6	V	1
Supply Voltage (SDRAM, Ethernet)	SV_DD	0 to +2.7	V
PLL Supply Voltage	AV_DD	0 to +1.65	V	2
SDRAM PLL Supply Voltage	SAV_DD	0 to +1.65	V	2
Input Voltage (3.3V LVTTL receivers)	V_IN	0 to +3.6	V
Storage Temperature Range	T_STG	-55 to +150
Case temperature under bias	T_C	-40 to +125		3

Notes:
1. If OV_DD 0.4V, it is required that V_DD 0.4V. Supply excursions not meeting this criteria must be limited to less than 25ms duration during each power up or power down event.
2. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440EP. A separate filter, as shown below, is recommended for each voltage:

3. This value is not a specification of the operational temperature range, it is a stress rating only.

PPC440EP Features

• PowerPC^® 440 processor core operating up to 667MHz with 32KB I-cache and D-cache with parity checking.
• Selectable processor:bus clock ratios of N:1, N:2.
• Floating Point Unit with single- and doubleprecision and single-cycle throughput.
• Dual bridged Processor Local Buses (PLBs) with 64- and 128-bit widths.
• Double Data Rate (DDR) Synchronous DRAM (SDRAM) interface operating up to 133MHz with ECC.
• DMA support for external peripherals, internal UART and memory.
• PCI V2.2 interface (3.3V only). Thirty-two bits at up to 66MHz.
• Programmable interrupt controller supports interrupts from a variety of sources.
• Programmable General Purpose Timers (GPT).
• Two Ethernet 10/100Mbps half- or full-duplex interfaces. Operational modes supported are MII, RMII, and SMII with packet reject.
• Up to four serial ports (16750 compatible UART).
• Two USB ports. One USB 1.1 Host interface with on-chip PHY. One USB 2.0 Device interface, with dedicated DMA, configured as a 1.1 on-chip PHY or a 2.0 UTMI.
• External peripheral bus (16-bit data) for up to six devices with external mastering.
• Two IIC interfaces (one with boot parameter read capability).
• NAND Flash interface.
• SPI interface.
• General Purpose I/O (GPIO) interface.
• JTAG interface for board level testing.
• Boot from PCI memory, NOR Flash on the external peripheral bus, or NAND Flash on the NAND Flash interface.
• Available in RoHS compliant lead-free package.

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