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SA-1100, SA-1100-DA, SA1100-JD3576

Table of contents:
Info of SA-1100
Info of SA-1100-DA
Info of SA1100-JD3576

SA-1100, SA-1100-DA, SA1100-JD3576 Selling Leads, Datasheet

MFG:INTEL Package Cooled:INTEL D/C:00+

SA-1100, SA-1100-DA, SA1100-JD3576 Picture

SA-1100, SA-1100-DA, SA1100-JD3576 Datasheet download

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Part Number: SA-1100

MFG: INTEL

Package Cooled: INTEL

D/C: 00+

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SA-1100 General Description

The SA-1100 is a general-purpose, 32-bit RISC microprocessor with a 16 Kbyte instruction cache (Icache), an 8 Kbyte write-back data cache (Dcache), a minicache, a write buffer, a read buffer, an MMU, an LCD controller, and serial I/O combined in a single chip. The SA-1100 provides powermanagement functionality and offers further power savings and integration by including oscillators and PLLs on-chip. The SA-1100 delivers both extensive system integration and high-end desktop performance without sacrificing power or price, making the SA-1100 a choice for many portable systems.

SA-1100 Features

The Intel^® StrongARM^® SA-1100 Microprocessor (SA-1100) is a device targeted to provide portable applications with high-end computing performance without requiring users to sacrifice available battery time. The SA-1100 incorporates a 32-bit StrongARM^® RISC processor running at 133/190 MHz with instruction and data cache, memory-management unit (MMU), and read/write buffers. In addition, the SA-1100 provides system support logic, multiple serial communication channels, a color/gray scale LCD controller, PCMCIA support for up to two sockets, and generalpurpose I/O ports.

` High performance
-150 Dhrystone 2.1 MIPS @ 133 MHz
-220 Dhrystone 2.1 MIPS @ 190 MHz
` 208-pin thin quad flat pack (LQFP)
` 256 mini-ball grid array (mBGA)
` Low power (normal mode)†
-<230 mW @1.5 V/133 MHz
-<330 mW @1.5 V/190 MHz
` 32-way set-associative caches
-16 Kbyte instruction cache
-8 Kbyte write-back data cache
` Integrated clock generation
-Internal phase-locked loop (PLL)
-3.686-MHz oscillator
-32.768-kHz oscillator
` 32-entry MMUs
-Maps 4 Kbyte, 8 Kbyte, or 1 Mbyte
` Power-management features
-Normal (full-on) mode
-Idle (power-down) mode
-Sleep (power-down) mode
` Write buffer
-8-entry, between 1 and 16 bytes each
` Big and little endian operating modes n Read buffer
-4-entry, 1, 4, or 8 words
` 3.3-V I/O interface n Memory bus
-Interfaces to ROM, Flash, SRAM, and DRAM
-Supports two PCMCIA sockets

† Power dissipation, particularly in idle mode, is strongly dependent on the details of the system design

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