SCAN90CP02VY, SCAN921025H, SCAN921226H Selling Leads, Datasheet
MFG:NS Package Cooled:LQFP32 D/C:812
SCAN90CP02VY, SCAN921025H, SCAN921226H Datasheet download
Part Number: SCAN90CP02VY
MFG: NS
Package Cooled: LQFP32
D/C: 812
MFG:NS Package Cooled:LQFP32 D/C:812
SCAN90CP02VY, SCAN921025H, SCAN921226H Datasheet download
MFG: NS
Package Cooled: LQFP32
D/C: 812
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Datasheet: SCAN90CP02VY
File Size: 267624 KB
Manufacturer: NSC [National Semiconductor]
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PDF/DataSheet Download
Datasheet: SCAN921025H
File Size: 523986 KB
Manufacturer: NSC [National Semiconductor]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: SCAN921226H
File Size: 523986 KB
Manufacturer: NSC [National Semiconductor]
Download : Click here to Download
The SCAN921025H transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The
SCAN921226H receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and recovers parallel clock.
Both devices are compliant with IEEE 1149.1 Standard for Boundary Scan Test. IEEE 1149.1 features provide the design or test engineer access via a standard Test Access Port (TAP) to the backplane or cable interconnects and the ability to verify differential signal integrity. The pair of devices also features an at-speed BIST mode which allows the interconnects between the Serializer and Deserializer to be verified at-speed.
The SCAN921025H transmits data over backplanes or cable. The single differential pair data path makes PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. Since one output transmits clock and data bits serially, it eliminates clock-to-data and data-to-data skew. The powerdown pin saves power by reducing supply current when not using either device. Upon power up of the Serializer, you can choose to activate synchronization mode or allow the Deserializer to use the synchronization-to-random-data feature. By using the synchronization mode, the Deserializer will
establish lock to a signal within specified lock times. In
addition, the embedded clock guarantees a transition on the
bus every 12-bit cycle. This eliminates transmission errors
due to charged cable conditions. Furthermore, you may put
the SCAN921025H output pins into TRI-STATE to achieve a
high impedance state. The PLL can lock to frequencies
between 20 MHz and 80 MHz.
The SCAN921025H transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The
SCAN921226H receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and recovers parallel clock.
Both devices are compliant with IEEE 1149.1 Standard for Boundary Scan Test. IEEE 1149.1 features provide the design or test engineer access via a standard Test Access Port (TAP) to the backplane or cable interconnects and the ability to verify differential signal integrity. The pair of devices also features an at-speed BIST mode which allows the interconnects between the Serializer and Deserializer to be verified at-speed.
The SCAN921025H transmits data over backplanes or cable. The single differential pair data path makes PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. Since one output transmits clock and data bits serially, it eliminates clock-to-data and data-to-data skew. The powerdown pin saves power by reducing supply current when not using either device. Upon power up of the Serializer, you can choose to activate synchronization mode or allow the Deserializer to use the synchronization-to-random-data feature. By using the synchronization mode, the Deserializer will
establish lock to a signal within specified lock times. In
addition, the embedded clock guarantees a transition on the
bus every 12-bit cycle. This eliminates transmission errors
due to charged cable conditions. Furthermore, you may put
the SCAN921025H output pins into TRI-STATE to achieve a
high impedance state. The PLL can lock to frequencies
between 20 MHz and 80 MHz.