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SCANH16602SM, SCANPSC100F, SCANPSC100FDMQB

Table of contents:
Info of SCANH16602SM
Info of SCANPSC100F
Info of SCANPSC100FDMQB

SCANH16602SM, SCANPSC100F, SCANPSC100FDMQB Selling Leads, Datasheet

MFG:NSC Package Cooled:NS D/C:02+

SCANH16602SM, SCANPSC100F, SCANPSC100FDMQB Picture

SCANH16602SM, SCANPSC100F, SCANPSC100FDMQB Datasheet download

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Part Number: SCANH16602SM

MFG: NSC

Package Cooled: NS

D/C: 02+

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SCANPSC100F General Description

The SCANPSC100F is designed to interface a generic parallel processor bus to a serial scan test bus. It is useful in improving scan throughput when applying serial vectors to system test circuitry and reduces the software overhead that is associated with applying serial patterns with a parallel processor. The SCANPSC100F operates by serializing data from the parallel bus for shifting through the chain of 1149.1 compliant components (i.e., scan chain). Scan data
returning from the scan chain is placed on the parallel port to be read by the host processor. Up to two scan chains can be directly controlled with the SCANPSC100F via two independent TMS pins. Scan control is supplied with user specific patterns which makes the SCANPSC100F protocol-independent. Overflow and underflow conditions are prevented by stopping the test clock. A 32-bit counter is used to program the number of TCK cycles required to
complete a scan operation within the boundary scan chain or to complete a SCANPSC100F Built-In Self Test (BIST) operation. SCANPSC100F device drivers and 1149.1 embedded test application code are available with Fairchild's SCAN Ease software tools.

SCANPSC100F Maximum Ratings

Supply Voltage (V_CC)                                                                         −0.5V to +7.0V
DC Input Diode Current (I_IK)
V_I = −0.5V                                                                                         −20 mA
V_I = V_CC                                                                                            + 0.5V +20 mA
DC Input Voltage (V_I)                                                                        −0.5V to V_CC+0.5V
DC Output Diode Current (I_OK)
V_O = −0.5V                                                                                       −20 mA
V_O= V_CC+ 0.5V                                                                                 +20 mA
DC Output Voltage (V_O)                                                                     −0.5V to V_CC + 0.5V
DC Output Source/Sink Current (I_O)                                                  ±50 mA
DC V_CC or Ground Current                                                                 ±50 mA
per Output Pin
DC Latchup Source or Sink Current                                                   ±300 mA
Junction Temperature
SOIC                                                                                                 +140°C
Storage Temperature                                                                      −65°C to +150°C
ESD Last Passing Voltage (Min) 4000V

SCANPSC100F Features

Compatible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture
Supported by Fairchild's SCAN Ease (Embedded Application Software Enabler) Software
Uses generic, asynchronous processor interface; compatible with a wide range of processors and PCLK frequencies
Directly supports up to two 1149.1 scan chains
16-bit Serial Signature Compaction (SSC) at the Test Data In (TDI) port
  Automatically produces pseudo-random patterns at the Test Data Out (TDO) port
  Fabricated on FACT^TM 1.5 m CMOS process
  Supports 1149.1 test clock (TCK) frequencies up to 25 MHz
  TTL-compatible inputs; full-swing CMOS outputs with 24 mA source/sink capability

SCANPSC100F Connection Diagram

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