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SCANPSC110FSC, SCANPSC110FSCX, SCANSTA101

Table of contents:
Info of SCANPSC110FSC
Info of SCANPSC110FSCX
Info of SCANSTA101

SCANPSC110FSC, SCANPSC110FSCX, SCANSTA101 Selling Leads, Datasheet

MFG:Fairchild Semiconductor Category:Integrated Circuits (ICs) Package Cooled:SMD28 D/C:05+

SCANPSC110FSC, SCANPSC110FSCX, SCANSTA101 Datasheet download

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Part Number: SCANPSC110FSCX

Category: Integrated Circuits (ICs)

MFG: Fairchild Semiconductor

Package Cooled: SMD28

D/C: 05+

Description: IC BRIDGE HIERARCH ADDRSS 28SOIC

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SCANPSC110FSCX Parameters

Technical/Catalog Information	SCANPSC110FSCX
Vendor	Fairchild Semiconductor
Category	Integrated Circuits (ICs)
Applications	*
Interface	*
Voltage - Supply	*
Package / Case	*
Packaging	*
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	SCANPSC110FSCX SCANPSC110FSCX

SCANSTA101 General Description

The SCANSTA101 is designed to function as a test master for a IEEE 1149.1 test system. The minimal requirements to create a tester are a microcomputer (uP, RAM/ROM, clock, etc.), SCANEASE r2.0 software, and a STA101.

The SCANSTA101 is an enhanced version of, and replacement for, the SCANPSC100. The additional features of the STA101 further allow it to offload some of the processor overhead while remaining flexible. The device architecture supports IEEE 1149.1, BIST, and IEEE 1532. The flexibility will allow it to adapt to any changes that may occur in 1532 and support yet unknown variants.

The SCANSTA101 is useful in improving vector throughput when applying serial vectors to system test circuitry and reduces the software overhead that is associated with applying serial patterns with a parallel processor. The SCANSTA101 features a generic Parallel Processor Interface (PPI) which operates by serializing data from the parallel bus for shifting through the chain of 1149.1 compliant components (i.e., scan chain). Writes can be controlled either by wait states or the ^DTACK line. Handshaking is accomplished with either polling or interrupts.

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
SCANSTA101SM	CMOS7	0	16561	0	0	954000	4	270700104
SCANSTA101SMX	CMOS7	0	16561	0	0	954000	4	270700104

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.

Design Tools

Title	Size in Kbytes	Date
SCANEASE software assists users in developing embedded IEEE1149.1 (JTAG) solutions using the SCANSTA101 JTAG Master	2572 Kbytes	3-Dec-2008	View	Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

SCANSTA101 Maximum Ratings

Temperature Min	-40 deg C
Temperature Max	85 deg C
View Using Catalog

SCANSTA101 Features

Compatible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture
Supported by National's SCAN Ease (Embedded Application Software Enabler) Software Rev 2.0
Available as a Silicon Device and Intellectual Property (IP) model for embedding into VLSI devices
Uses generic, asynchronous processor interface; compatible with a wide range of processors and PCLK frequencies
16-bit Data Interface (IP scalable to 32-bit)
2Kx32 bit dual-port memory addressing for access by the PPI or the 1149.1 master
Load-on-the-fly (LotF) and Preload operating modes supported
On-Board Sequencer allows multi-vector operations such as those required to load data into an FPGA
On-Board Compares support TDI validation against preloaded expected data
32-bit Linear Feedback Shift Register (LFSR) at the Test Data In (TDI) port
State, Shift, and BIST macros allow predetermined TMS sequences to be utilized
Operates at 3.3v supply voltages w/ 5V tolerant I/O
Outputs support Power-Down TRI-STATE mode.

SCANSTA101 Connection Diagram

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