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TSB21LV03C, TSB24B40AVFN, TSB2598PC

Table of contents:
Info of TSB21LV03C
Info of TSB24B40AVFN
Info of TSB2598PC

TSB21LV03C, TSB24B40AVFN, TSB2598PC Selling Leads, Datasheet

MFG:TI Package Cooled:QFP D/C:06+

TSB21LV03C, TSB24B40AVFN, TSB2598PC Picture

TSB21LV03C, TSB24B40AVFN, TSB2598PC Datasheet download

Five Points

Part Number: TSB21LV03C

MFG: TI

Package Cooled: QFP

D/C: 06+

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TSB21LV03C General Description

The TSB21LV03C provides the analog and digital physical layer functions needed to implement a three-port node in a cable-based IEEE 1394-1995 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB21LV03C is designed to interface with a link-layer controller (LLC), such as the TSB12LV21, TSB12LV31, TSB12C01, TSB12LV22, TSB12LV41, or TSB12LV01.

The TSB21LV03C requires either an external 24.576-MHz crystal or crystal oscillator. The internal oscillator drives an internal phase-locked loop (PLL), which generates the required 196.608-MHz reference signal. The 196.608-MHz reference signal is internally divided to provide the 49.152/98.304-MHz clock signals that control transmission of the outbound encoded strobe and data information. The 49.152-MHz clock signal is also supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. For the TSB21LV03C, the 49.152 MHz clock output is active whenRESET is asserted low. The power-down function, when enabled by taking the PD terminal high, stops operation of the PLL and disables all circuitry except the cable-not-active signal circuitry.

The TSB21LV03C supports an optional isolation barrier between itself and its LLC. When ISO is tied high, the link interface outputs behave normally. Also, when ISO is tied high, the internal bus hold function is enabled for use with the TI Bus Holder isolation. TI bus holder isolation is implemented when ISO is tied high.

TSB21LV03C Maximum Ratings

Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDD+0.5 V
Output voltage range at any output, VO . . . . . . . . . . .0.5 V to VDD+0.5V
Continuous total power dissipation . . . . . .   See Dissipation Rating Table
Operating free-air temperature, TA, TSB21LV03C . . . . . . . . . . . 0 to 70
                                                        TSB21LV03CI . . . . . . . . 40 to 85
                                                       TSB21LV03CM . . . . . . . 55 to 125
Junction temperature, TJ, PM package . . . . . . . . . . . . . . . . . . . . . . . .150
                                        HV package . . . . . . . . . . . . . . . . . . . . . . . .165
Storage temperature range, Tstg . . . . . . . . . . . . . . . . .   . . . 65 to 150
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . .220
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated onditions for extended periods may affect device reliability.

TSB21LV03C Features

·Fully Interoperable with FireWireE and i.LINKE Implementation of IEEE 1394-1995
·Provides Three Fully Compliant Cable Ports at 100/200 Megabits per Second (Mbits/s)
·Cable Ports Monitor Line Conditions for Active Connection to Remote Node
·Device Power-Down Feature to Conserve Energy in Battery-Powered Applications
·Inactive Ports Disabled to Save Power
·Logic Performs System Initialization and Arbitration Functions
·Encode and Decode Functions Included for Data-Strobe Bit-Level Encoding
·Incoming Data Resynchronized to Local Clock
·Single 3.3-V Supply Operation
·Interface to Link-Layer Controller Supports Low Cost TIE Bus-Holder Isolation
·Data Interface to Link-Layer Controller Provided Through 2/4 Parallel Lines at 49.152 MHz
·Low Cost 24.576-MHz Crystal Oscillator and PLL Provide Transmit/Receive Data at 100/200 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz
·Interoperable with 1394 Link-Layer Controllers Using 5-V Supplies
·Interoperable Across 1394 Cable with 1394 Physical Layers (Phy) Using 5-V Supplies
·Node Power-Class Information Signaling for System Power Management
·Cable Power Presence Monitoring
·Separate Cable Bias and Driver Termination Voltage Supply for Each Port
·High Performance 64-Pin TQFP (PM) Package and 68-Pin CFP (HV) Package

TSB21LV03C Connection Diagram

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