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The TSB43AA82 is a high performance 1394 integrated PHY and link layer controller. It is compliant with the IEEE 1394-1995 and IEEE 1394a-2000 specifications and supports asynchronous transfers.
TSB43AA82 has a generic 16-/8-bit host bus interface. It supports parallel or multiplexed connections to the microcontroller (MCU) at rates up to 40 MHz.
The TSB43AA82 offers large data transfers with three mutually independent FIFOs: 1) the asynchronous command FIFO with 1512 Bytes, 2) the DMA FIFO with 4728 bytes and 3) the Config ROM/LOG FIFO with 504 bytes.
The features of the TSB43AA82 support the serial bus protocol 2 (SBP-2). It handles up to four initiators with the SBP-2 transaction/timer manager. This SBP-2 transaction engine supports fully automated operation request block (ORB) fetches and fully automated memory page table fetches for both read and write transactions. Automated responses to other node requests are provided; this includes responding to another node's read request to the Config ROM and issuing ack_busy_X for a single retry. Various control registers enable the user to program IEEE 1394 asynchronous transaction settings. The user can program the number of retries and the split transaction time-out value by setting the time limit register in the CFR.
The TSB43AA82 also supports the direct print protocol (DPP). The asynchronous receive FIFO (ARF) in the TSB43AA82 is large enough to satisfy the connection register area, the DRF receiving FIFO can be used as the segment data unit (SDU) register to fulfill the large data transfer.
This document is not intended to serve as a tutorial on IEEE 1394; users are referred to IEEE Std 1394-1995 and IEEE 1394a-2000 (see Note 1).
TSB43AA82 Features
• IEEE 1394a-2000 Compliant • Single 3.3-V Supply • Internal 1.8-V Circuit to Reduce Power Consumption • Integrated 400-Mbps Two-Port Physical Layer (PHY) • Internal Voltage Regulator • IEEE 1394 Related Functions: − Automated Read Response for ConfigROM Register Access − Automated Single Retry Protocol and Split Transaction Control • SBP-2 Related Functions: − Supports Four Initiators by Automated Transactions and More Can Be Supported Through Firmware. − Automated Management ORB Fetching − Automated Linked Command ORB Fetching − Automated PageTable Fetching − Automated Status Block Transmit • Ability to Support Direct Print Protocol (DPP) Mode • Data Transfers: − Auto Address Increment of Direct/Indirect Addressing on Data Transfer (Packetizer) − Automated Header Insert/Strip for DMA Data Transfers − 8-/16-Bit Asynchronous and Synchronous DMA I/F With Handshake and Burst Mode − Supports ATAPI (Ultra-DMA) Mode and SCSI Mode − 8-/16-Bit Data/Address Multiplex Microcontroller and 8-/16-Bit Separated Data/Address Bus − Three FIFO Configurations That Support High Performance for the DMA and for Command Exchanges Asynchronous Command FIFO: 1512 Bytes Config ROM/LOG FIFO: 504 Bytes DMA FIFO: 4728 Bytes • Multiple Package Options: − PGE Dual 1394 Port Package, 144-Terminal Plastic Quad Flatpack − GGW Commercial Dual 1394 Port Package, 176-Terminal BGA − GGW Industrial Dual 1394 Port Package (TSB43AA82I), 176-Terminal BGA With Operational Range From −40°C to 85°C
TSB43AA82 Connection Diagram
TSB43AA82A General Description
The TSB43AA82A is a high performance 1394 integrated PHY and link layer controller. It is compliant with the IEEE 1394-1995 and IEEE 1394a-2000 specifications and supports asynchronous transfers.
TSB43AA82A has a generic 16-/8-bit host bus interface. It supports parallel or multiplexed connections to the microcontroller (MCU) at rates up to 40 MHz.
The TSB43AA82A offers large data transfers with three mutually independent FIFOs: 1) the asynchronous command FIFO with 1512 Bytes, 2) the DMA FIFO with 4728 bytes and 3) the Config ROM/LOG FIFO with 504 bytes.
The features of the TSB43AA82A support the serial bus protocol 2 (SBP-2). It handles up to four initiators with the SBP-2 transaction/timer manager. This SBP-2 transaction engine supports fully automated operation request block (ORB) fetches and fully automated memory page table fetches for both read and write transactions. Automated responses to other node requests are provided; this includes responding to another node's read request to the Config ROM and issuing ack_busy_X for a single retry. Various control registers enable the user to program IEEE 1394 asynchronous transaction settings. The user can program the number of retries and the split transaction time-out value by setting the time limit register in the CFR.
The TSB43AA82A also supports the direct print protocol (DPP). The asynchronous receive FIFO (ARF) in the TSB43AA82A is large enough to satisfy the connection register area, the DRF receiving FIFO can be used as the segment data unit (SDU) register to fulfill the large data transfer.
This document is not intended to serve as a tutorial on IEEE 1394; users are referred to IEEE Std 1394-1995 and IEEE 1394a-2000 (see Note 1).
TSB43AA82A Maximum Ratings
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . 0.5 V to VDD+0.5 V Output voltage range at any output, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDD+0.5 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation table Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground.
TSB43AA82A Features
• IEEE 1394a-2000 Compliant • Single 3.3-V Supply • Internal 1.8-V Circuit to Reduce Power Consumption • Integrated 400-Mbps Two-Port Physical Layer (PHY) • Internal Voltage Regulator • IEEE 1394 Related Functions: Automated Read Response for ConfigROM Register Access Automated Single Retry Protocol and Split Transaction Control • SBP-2 Related Functions: Supports Four Initiators by Automated Transactions and More Can Be Supported Through Firmware. Automated Management ORB Fetching Automated Linked Command ORB Fetching Automated PageTable Fetching Automated Status Block Transmit • Ability to Support Direct Print Protocol (DPP) Mode • Data Transfers: Auto Address Increment of Direct/Indirect Addressing on Data Transfer (Packetizer) Automated Header Insert/Strip for DMA Data Transfers 8-/16-Bit Asynchronous and Synchronous DMA I/F With Handshake and Burst Mode Supports ATAPI (Ultra-DMA) Mode and SCSI Mode 8-/16-Bit Data/Address Multiplex Microcontroller and 8-/16-Bit Separated Data/Address Bus Three FIFO Configurations That Support High Performance for the DMA and for Command Exchanges Asynchronous Command FIFO: 1512 Bytes Config ROM/LOG FIFO: 504 Bytes DMA FIFO: 4728 Bytes