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TUSB2551RGTR, TUSB3200, TUSB3200A

Table of contents:
Info of TUSB2551RGTR
Info of TUSB3200
Info of TUSB3200A

TUSB2551RGTR, TUSB3200, TUSB3200A Selling Leads, Datasheet

MFG:Texas Instruments (VA) Category:Integrated Circuits (ICs) Package Cooled:QFN D/C:09+

TUSB2551RGTR, TUSB3200, TUSB3200A Picture

TUSB2551RGTR, TUSB3200, TUSB3200A Datasheet download

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Part Number: TUSB2551RGTR

Category: Integrated Circuits (ICs)

MFG: Texas Instruments (VA)

Package Cooled: QFN

D/C: 09+

Description: IC ADVANCED USB TXRX 16-QFN

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TUSB2551RGTR Parameters

Technical/Catalog Information	TUSB2551RGTR
Vendor	Texas Instruments (VA)
Category	Integrated Circuits (ICs)
Number of Drivers/Receivers	-
Type	USB Transceiver
Voltage - Supply	1.65 V ~ 3.6 V
Package / Case	16-QFN
Packaging	Digi-Reel?
Protocol	USB 2.0
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	TUSB2551RGTR TUSB2551RGTR 296 23623 6 ND 296236236ND 296-23623-6

TUSB3200 Maximum Ratings

Supply voltage range, DV_DD . . . . .. . .. . . . . . . . . . . . . . . . . . . 0.5 to 3.6 V
                                    DV_DDS . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 to 5.5 V
                                    AV_DD . . . . .. . . . . . . . . . . . . . . . . . . . . . 0.5 to 3.6 V
Input voltage range, V_I: 3.3-V TTL/LVCMOS . . . . . . . 0.5 V to DV_DD + 0.5 V
5-V Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to DV_DDS + 0.5 V
5-V3.3-V TTL level shifting   . . . . . . . . . . . . . . . . . 0.5 V to DV_DDS+ 0.5 V
Output voltage range, V_O: 3.3-V TTL/LVCMOS . . . . . 0.5 V to DV_DD + 0.5 V
5-V Compatible . . . . . . . . . . . . . . . . . . . . .. . . . . . 0.5 V to DV_DDS + 0.5 V
3.3-V5-V TTL level shifting   . . . . . .. . . . . . . . . . . . 0.5 V to DV_DDS + 0.5 V
3.3-V5-V CMOS level shifting . . . . . . . . . . . . . . . . 0.5 V to DV_DDS + 0.5 V
Input clamp current, I_IK (V_I< 0 or VI > DVDD) . . . .. . . . . . . . . . . . . . ±20 mA
Output clamp current, I_OK (V_O < 0 or V_O > DVDD) . . . . . . . . . . . . . . ±20 mA
Storage temperature range, T_stg . . . . . . . . . . . .. . . . . . . . . 65 to 150
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

TUSB3200 Features

• USB Specification version 1.1 compatible
• USB Audio Class Specification 1.0 compatible
• Integrated USB transceiver
• Supports 12 Mb/s data rate (full speed)
• Supports suspend/resume and remote wake-up
• Supports control, interrupt, bulk and isochronous data transfer types
• Supports up to a total of 7 in endpoints and 7 out endpoints in addition to the control endpoint
• Data transfer type, data buffer size, single or double buffering is programmable for each Endpoint
• On-Chip adaptive clock generator (ACG) supports asynchronous, synchronous and adaptive synchronization modes for isochronous endpoints
• To support synchronization for streaming USB audio data, the ACG can be used to generate the master clock for the CODEC

TUSB3200 Connection Diagram

TUSB3200A General Description

2.1 Architectural Overview

2.1.1 Oscillator and PLL
Using an external 6-MHz crystal, the TUSB3200A derives the fundamental 48-MHz internal clock signal using an on-chip oscillator and PLL. Using the PLL output, the other required clock signals are generated by the clock generator and adaptive clock generator.

2.1.2 Clock Generator and Sequencer Logic
Utilizing the 48-MHz input from the PLL, the clock generator logic generates all internal clock signals, except for the codec port interface master clock (MCLK) and serial clock (CSCLK) signals. The TUSB3200A internal clocks include the 48-MHz clock, a 24-MHz clock, a 12-MHz clock and a USB clock. The USB clock also has a frequency of 12-MHz.The USB clock is the same as the 12-MHz clock when the TUSB3200A is transmitting data and is derived from the data when the TUSB3200A is receiving data. To derive the USB clock when receiving USB data, the TUSB3200A utilizes an internal digital PLL (DPLL) that uses the 48-MHz clock.The sequencer logic controls the access to the SRAM used for the USB endpoint configuration blocks and the USB endpoint buffer space. The SRAM can be accessed by the MCU, USB buffer manager (UBM) or DMA channels. The sequencer controls the access to the memory using a round robin fixed priority arbitration scheme. This basically means that the sequencer logic generates grant signals for the MCU, UBM and DMA channels at a predetermined fixed frequency.

2.2 Device Operation
The operation of the TUSB3200A is explained in the following sections. For additional information on USB, refer to the universal serial bus Specification version 1.1.

2.2.1 Clock Generation
The TUSB3200A requires an external 6-MHz crystal and PLL loop filter components connected as shown in Figure 4-1 to derive all the clocks needed for both USB and codec operation. Using the low frequency 6-MHz crystal and generating the required higher frequency clocks internal to the IC is a major advantage regarding EMI.

2.2.2 Device Initialization
After a power-on reset is applied to the TUSB3200A device, the 8052 MCU will execute a boot loader program from the 4K byte boot ROM mapped to the program memory space. During device initialization, the boot loader program downloads the application program code from an external EEPROM through the I2C interface. This requires that a binary image of the application code be written to the 8K byte code RAM in the TUSB3200A device.All memory mapped registers are initialized to a default value as defined in Appendix A, MCU Memory and Memory-Mapped Registers. The TUSB3200A device powers up with a default function address of zero and disconnected from the USB.

TUSB3200A Maximum Ratings

Supply voltage range, DV_DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 to 3.6 V
                                   DV_DDS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 to 5.5 V
                                   AV_DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 to 3.6 V
Input voltage range, V_I: 3.3-V TTL/LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..0.5 V to DV_DD + 0.5 V
                                          5-V Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to DV_DDS + 0.5 V
                                           5-V3.3-V TTL level shifting . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to DV_DDS+ 0.5 V
Output voltage range, V_O: 3.3-V TTL/LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to DV_DD + 0.5 V
                                           5-V Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to DV_DDS + 0.5 V
                                           3.3-V5-V TTL level shifting . . . . . . . . . . . . . . . . . . . . . . 0.5 V to DV_DDS + 0.5 V
                                           3.3-V5-V CMOS level shifting . . . . . . . . . . . . . . . . . . . . 0.5 V to DV_DDS + 0.5 V
Input clamp current, I_IK (V_I < 0 or V_I > DV_DD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, I_OK(V_O < 0 or V_O > DV_DD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   ±20 mA
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C

TUSB3200A Features

• Universal Serial Bus (USB)
   • USB Specification version 1.1 compatible
   • USB Audio Class Specification 1.0 compatible
   • Integrated USB transceiver
   • Supports 12 Mb/s data rate (full speed)
   • Supports suspend/resume and remote wake-up
   • Supports control, interrupt, bulk and isochronous data transfer types
   • Supports up to a total of 7 in endpoints and 7 out endpoints in addition to the control endpoint
   • Data transfer type, data buffer size, single or double buffering is programmable for each endpoint
   • On-chip adaptive clock generator (ACG) supports asynchronous, synchronous and adaptive synchronization modes for isochronous endpoints
   • To support synchronization for streaming USB audio data, the ACG can be used to generate the master clock for the codec
• Micro-Controller Unit (MCU)
   • Standard 8052 8-bit core
   • 4K Bytes of program memory ROM that contains a boot loader program that loads the application firmware from external EEPROM
   • 8K Bytes of program memory RAM which is loaded by the boot loader program
   • 256 Bytes of internal data memory RAM
   • Two GPIO ports
   • MCU handles all USB control, interrupt and bulk endpoint transfers
• DMA Controller
   • Four DMA channels to support streaming USB audio data to/from the codec port interface
   • Each channel can support a single USB isochronous endpoint
   • For I²S modes, either a single or multiple USB isochronous endpoints can be used to support multiple DACs/ADCs
• Codec Port Interface
   • Configurable to support AC'97 1.X, AC'97 2.X or I²S serial interface formats
   • I²S modes can support a combination of up to 4 DACs and/or 3 ADCs
   • Can be configured as a general-purpose serial interface
• I²C Interface
   • Master only interface
   • Does not support a multimaster bus environment
   • Programmable to 100 kbit/s or 400 kbit/s data transfer speeds
• Pulse Width Modulation (PWM) Output
   • Programmable frequency range from 732.4 Hz to 93.75 kHz
   • Programmable duty cycle
• General Characteristics
   • Available in a 52-Pin TQFP Package
   • On-chip phase-locked loop (PLL) with internal oscillator is used to generate internal clocks from a 6 MHz crystal input
   • 3.3-V core and 5-V compatible input/output buffers used for codec port interface
   • Reset output available which is asserted for both system and USB reset
   • External MCU mode supports application firmware development

TUSB3200A Connection Diagram

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