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UA1E, UA2001AF, UA2003C

Table of contents:
Info of UA1E
Info of UA2001AF
Info of UA2003C

UA1E, UA2001AF, UA2003C Selling Leads, Datasheet

MFG:Atmel Package Cooled:MSOP D/C:2010+

UA1E, UA2001AF, UA2003C Datasheet download

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Part Number: UA1E

MFG: Atmel

Package Cooled: MSOP

D/C: 2010+

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UA1E General Description

The UA1E series of ULCs is well suited for conversion of large sized CPLDs and FPGAs. We can support within one ULC from 18 Kbits to 390 Kbits DPRAM and from 46 Kgates to 780 Kgates. Typically, ULC die size is 50% smaller than the equivalent FPGA die size. DPRAM blocks are compatible with Xilinx or Altera FPGA blocks.

Devices are implemented in highperformance CMOS technology with 0.35m (drawn) channel lengths, and are capable of supporting flipflop toggle rates of 200 MHz at 3.3V and 180 MHz at 2.5V, and input to output delays as fast as 150ps at 3.3V. The architecture of the UA1E series allows for efficient conversion of many PLD architecture and FPGA device types with higher IO count. A compact RAM cell, along with the large number of available gates allows the implementation of RAM in FPGA architectures that support this feature, as well as JTAG boundaryscan and scanpath testing.

Conversion to the UA1E series of ULC can provide a significant reduction in operating power when compared to the original PLD or FPGA. This is especially true when compared to many PLD and CPLD architecture devices, which typically consume 100mA or more even when not being clocked. The UA1E series has a very low standby consumption of 0.3nA/gate typically commercial temperature, which would yield a standby current of 42A on a 144,000 gates design. Operating consumption is a strict function of clock frequency, which typically results in a power reduction of 50% to 90% depending on the device being compared.

The UA1E series provides several options for output buffers, including a variety of drive levels up to 18mA. Schmitt trigger inputs are also an option. A number of techniques are used for improved noise immunity and reduced EMC emissions, including: several independent power supply busses and internal decoupling for isolation; slew rate limited outputs are also available if required.

The UA1E series is designed to allow conversion of high performance 3.3V devices as
well as 2.5V devices. Support of mixed supply conversions is also possible, allowing
optimal tradeoffs between speed and power consumption.

UA1E Maximum Ratings

Operating Temperature
Commercial..........................................................0° to 70°C
Industrial..........................................................-40° to 85°C
Max Supply Core Voltage (V_DD)..........................           3.6V
Max Supply Periphery Voltage (V_DD5).................          5.5V
Input Voltage (VIN)VDD............................................. +0.5V
5V Tolerant/Compliant V_DD5................................       +0.5V
Storage Temperature.................................... -65° to 150°C
Operating Ambient Temperature....................-55° to 125°C

UA1E Features

• High-performance ULC Family Suitable for Large-sized CPLDs and FPGAs
• From 46K Gates up to 780K Gates Supported
• From 18 Kbit to 390 Kbit DPRAM
• Compatible with Xilinx or Altera
• Pin-counts to Over 976 pins
• Any Pinout Matched
• Full Range of Packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, BGA, PGA/PPGA
• Low Quiescent Current: 0.3 nA/gate
• Available in Commercial and Industrial Grades
• 0.35 m Drawn CMOS, 3 and 4 Metal Layers
• Library Optimised for Synthesis, Floor Plan & Testability Generation (ATPG)
• High Speed Performances:
150 ps Typical Gate Delay @3.3V
Typical 600 MHz Toggle Frequency @3.3V
Typical 360 MHz Toggle Frequency @2.5V
• High System Frequency Skew Control:
Clock Tree Synthesis Software
• Low Power Consumption:
0.25 W/Gate/ MHz @3.3V
0.18 W/Gate/ MHz @2.5V
• Power on Reset (Internal)
• Standard 2, 4, 6, 8,10, 12 and 18mA I/Os
• CMOS/TTL/PCI LVCMOS, LVTTL, GTL, HSTL, LVDS Interfaces
• ESD (2 kV) and Latch-up Protected I/O
• High Noise & EMC Immunity:
I/O with Slew Rate Control
Internal Decoupling
Signal Filtering between Periphery & Core
• Thick oxide matrices allowing 5V Compliance
• Internal Regulator 5V -> 3.3V
• PLL 0.35m with Integrated Filter

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