UA2100

The UA2 series of ULCs is well suited for conversion of large sized CPLDs andFPGAs. Devices are implemented in highperformance CMOS technology with 0.25µm (drawn) channel lengths, and are capable of supporting flipflop toggle rates of 280 MHz at 2.5V, and input to output delay cells as fast as 100ps at 2.5V. The archi-tecture of the UA2 series allows for efficient conversion of many PLD architecture andFPGA device types with higher IO count. A compact RAM cell, along with the largenumber of available gates allows the implementation of RAM in FPGA architecturesthat support this feature, as well as JTAG boundaryscan and scanpath testing.

Conversion to the UA2 series of ULC can provide a significant reduction in operatingpower when compared to the original PLD or FPGA. This is especially true when com-pared to many PLD and CPLD architecture devices, which typically consume 100mAor more even when not being clocked. The UA2 series has a very low standby con-sumption of less than 0.3 nA/gate typically commercial temp, which would yield astandby current of 0.3 nA/gate, 0.42µA on a 144,000 gates design. Operating con-sumption is a strict function of clock frequency, which typically results in a powerreduction of 50% to 90% depending on the device being compared.

The UA2 series provides several options for output buffers, including a variety of drivelevels up to 18mA. Schmitt trigger inputs are also an option. A number of techniquesare used for improved noise immunity and reduced EMC emissions, including: severalindependent power supply busses and internal decoupling for isolation; slew rate lim-ited outputs are also available if required.