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VSC8117QP-T, VSC8120, VSC8121

Table of contents:
Info of VSC8117QP-T
Info of VSC8120
Info of VSC8121

VSC8117QP-T, VSC8120, VSC8121 Selling Leads, Datasheet

MFG:800 D/C:VITESSE

VSC8117QP-T, VSC8120, VSC8121 Datasheet download

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Part Number: VSC8117QP-T

MFG: 800

Package Cooled:

D/C: VITESSE

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VSC8121 General Description

The VSC8121 is a monolithic Phase Locked Loop (PLL) based clock generator designed for telecommunications systems operating at 2.5Gb/s. The VSC8121 incorporates a reactance-based (LC) Voltage Controlled Oscillator (VCO) with low phase noise. The PLL's loop filter is on-chip.

The device has a differential 2.488GHz CML clock output (CO/CON) signal, a single-ended TTL lowspeed clock (LSCLK) output equivalent in frequency to that of the reference clock, and a TTL reference clock input selectable for 51.84MHz, 77.76MHz or 155.52MHz. TTL inputs REFSEL[0:1] are used to make this selection.

A clean REFCLK signal is required since jitter below the PLL loop bandwidth, which is present on the REFCLK input, will appear on the output. Jitter on REFCLK at frequencies above the loop bandwidth will be attenuated by the PLL. The state of REFSEL[0:1] will select which frequency is expected on the REFCLK input.

VSC8121 Maximum Ratings

Power Supply Voltage (V_CC) Potential to GND ...........................-0.5 V to +4.0 V
TTL Input Voltage Applied ..........................................................-0.5 V to + 5.5V
Output Current (I_OUT) .............................................................................. 50 mA
Case Temperature Under Bias (T_C) .......................................... -55 to + 125
Storage Temperature (T_STG) .................................................... -65 to + 150

VSC8121 Features

• Monolithic Phase Locked Loop
• On-Chip LC Oscillator
• On-Chip Loop Filter
• TTL/CMOS Reference Clock
• Selectable Reference
• Jitter Meets SONET OC-48 and SDH STM-16 Requirements
• High-Speed CML Clock Output
• Single 3.3V Supply
• Compact 10mm x 10mm 44 Pin PQFP Package

VSC8121 Connection Diagram

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