29C512PD, 29C516E, 29C520CNS Selling Leads, Datasheet
MFG:ATMEL Package Cooled:PLCC 32 D/C:97+
29C512PD, 29C516E, 29C520CNS Datasheet download
Part Number: 29C512PD
MFG: ATMEL
Package Cooled: PLCC 32
D/C: 97+
29C512PD, 29C516E, 29C520CNS
- Table of contents:
Info of 29C512PD
Info of 29C516E
Info of 29C520CNS
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About 29C010
PDF/DataSheet Download
Datasheet: 29C010
File Size: 745074 KB
Manufacturer: ATMEL [ATMEL Corporation]
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About 29C516E
PDF/DataSheet Download
Datasheet: 29C516E
File Size: 96974 KB
Manufacturer: ATMEL [ATMEL Corporation]
Download : Click here to Download
About 29C010
PDF/DataSheet Download
Datasheet: 29C010
File Size: 745074 KB
Manufacturer: ATMEL [ATMEL Corporation]
Download : Click here to Download
29C516E General Description
The 29C516E Atmel EDAC is a very low power flowthrough 16bit Error Detection And Correction unit (EDAC) with two user data buses. The EDAC is used in a high integrity system for monitoring and correction of data values coming from the memory space. During a processor write cycle, at each memory location (16bit width), EDAC calculated checkword (6 or 8bit width) is added. When performing a read operation from memory, the 29C516E verifies the entire checkword and data combination. It detects and can correct 100% of all the singlebit errors and it detects all doublebit errors. When the 29C516E uses 6checkbit, it can detect any error on any single 4bit memory chip. The 8checkbit option gives the additional capability to detect all errors on any single 8bit memory chip. All the errors are signaled to the master system (via 2 error Flags) in order to allow the processor to make the required action.
The 29C516E operates in two possible modes: corrected or detected mode. In the corrected mode, the singlebit in error is complemented (corrected). Then, the available entire data is placed on the output port and the Correctable Error Flag is set. In case of doublebit errors (or more),the corrupted data is placed on the output port and the Uncorrectable Error Flag is set. Note that when there is more than two errors, then some bit patterns may appear as possible correctable errors. Therefore, if the environment produces this type of error, the EDAC must be used in detect and provide no automatic correction. Data and syndrome analysis must be done.
The 29C516E acts as a data buffer for µPmemory interfacing. A flowthrough EDAC is placed in the data bus path, between the processor and the memory to be protected. This component is able to serve two different users of one memory space. So, it forms the interface between the 22/24bit (16+6/16+8 memory data bus and the two 16bit processor data busses with a high drive capability (12.8 mA). The two data ports can be used to create a dual port bus in front of memory space. The User1(2) can transfer data from/to the memory or from/to the User2(1), bypassing the memory. During read or write memory cycles processed by the User1(2), the User2(1) have the possibility to listen the transferred data.
The 29C516E operates in two possible modes: corrected or detected mode. In the corrected mode, the singlebit in error is complemented (corrected). Then, the available entire data is placed on the output port and the Correctable Error Flag is set. In case of doublebit errors (or more),the corrupted data is placed on the output port and the Uncorrectable Error Flag is set. Note that when there is more than two errors, then some bit patterns may appear as possible correctable errors. Therefore, if the environment produces this type of error, the EDAC must be used in detect and provide no automatic correction. Data and syndrome analysis must be done.
The 29C516E acts as a data buffer for µPmemory interfacing. A flowthrough EDAC is placed in the data bus path, between the processor and the memory to be protected. This component is able to serve two different users of one memory space. So, it forms the interface between the 22/24bit (16+6/16+8 memory data bus and the two 16bit processor data busses with a high drive capability (12.8 mA). The two data ports can be used to create a dual port bus in front of memory space. The User1(2) can transfer data from/to the memory or from/to the User2(1), bypassing the memory. During read or write memory cycles processed by the User1(2), the User2(1) have the possibility to listen the transferred data.
29C516E Maximum Ratings
|
Parameter |
Value |
|---|---|
| Supply voltage, Vcc | 0.5 to 7V |
| Input voltage range | 0.5 to Vcc + 0.5 V |
| Input current per power pin | +/ 50 mA |
| Input current per signal pin | +/ 10 mA |
| Continuous output current, one pin | +/ 30 mA |
| Soldering lead temperature 1.6 mm from case for max 10 s | + 300 0C |
| Storage temperature | 65 0C to + 150 0C |
| Maximum package power dissipation | 1.0 W |
29C516E Features
Very Low Power CMOS
16Bit operation with 6 or 8 Check Bits
Fast Error Detection : 31 ns (max.)
Fast Error Correction : 32 ns (max.)
Corrects all SingleBit Errors
Detects all DoubleBit Errors
Detects some MultiBit Errors
Detects Chip Errors (x1, x4 & x8 RAM Format)
Correctable and Uncorrectable Error Flags
Two User Data Buses
User to User Transfer and Listening operation
High Drive Capability on Buses : 12.8 mA
TTL Compatible
Single 5V ±10% Power Supply
100 Pin Multilayer Quad Flat Pack(Flat leaded or L leaded).
16Bit operation with 6 or 8 Check Bits
Fast Error Detection : 31 ns (max.)
Fast Error Correction : 32 ns (max.)
Corrects all SingleBit Errors
Detects all DoubleBit Errors
Detects some MultiBit Errors
Detects Chip Errors (x1, x4 & x8 RAM Format)
Correctable and Uncorrectable Error Flags
Two User Data Buses
User to User Transfer and Listening operation
High Drive Capability on Buses : 12.8 mA
TTL Compatible
Single 5V ±10% Power Supply
100 Pin Multilayer Quad Flat Pack(Flat leaded or L leaded).
29C516E Connection Diagram
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