29C532E

The 29C532E EDAC is a very low power bus-watch 32-bit Error Detection And Correction unit (EDAC). EDAC is used in a high integrity system for monitoring d correcting data values coming from the memory  space. Such a bus-watch EDAC is connected as a peripheral on the data bus and watches on and controls the integrity of the data memory.

During a processor write cycle, at each memory location (32-bit width), EDAC calculated checkword (7 or 8-bit width) is added. When performing a read operation from memory, the 29C532E verifies the entire checkword and data combination. It detects and can correct 100% of all the single-bit errors and it detects all multi-bit errors but can not correct them. All the errors are reported to the master system to allow the processor to take action as required. In case of single-bit error, the Correctable ERRor flag is set and the single-bit in error is complemented (corrected). Then, the data can be substituted to the corrupted data on the system data bus. In case of multi-bit error, the Non-Correctable ERRor flag is set, the data can not be repaired. Note that when multi-bit errors occur, there are some bit patterns which may appear as possible correctable errors. Therefore, if the environment produces this type of error, the EDAC must be used in detect-only-without-correction configuration. Data and syndrome analysis must be rapidly done.

Because the 29C532E latches the data, byte or 16-bit word write operations are possible if they take place in a read-modify-write accesses to the memory space.

When the 29C532E uses 7-checkbit, it can detect any errors on any single 1 or 4-bit memory chip. The 8-checkbit option gives the additional capability to detect all errors on any 8-bit memory chip.