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ATU18, ATU2207B-MFPY, ATU2280B

Table of contents:
Info of ATU18
Info of ATU2207B-MFPY
Info of ATU2280B

ATU18, ATU2207B-MFPY, ATU2280B Selling Leads, Datasheet

MFG:Atmel Package Cooled:PC D/C:2010+

ATU18, ATU2207B-MFPY, ATU2280B Datasheet download

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Part Number: ATU18

MFG: Atmel

Package Cooled: PC

D/C: 2010+

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ATU18 General Description

The ATU18 series of ULCs are fully suited for conversion of latest CPLDs and FPGAs.It supports within one ULC 55Kbits to 847Kbits DPRAM and 45Kgates to 1000 Kgates. Typically, ULC die size is 50% smaller than the equivalent FPGA. Metal level customisation allows a DPRAM blocks compatibility with Xilinx® or Altera® blocks.

Devices are implemented in highperformance 0.18 um CMOS technology to improve the design frequency and reach 250Mhz typical application and local clock up to 400Mhz. The architecture of the ATU18 series is dedicated for efficient conversion of latest CPLD and FPGA device types with higher IO count. A compact RAM cell and a large number of available gates allow the implementation of memories compatible with FPGA RAM, as well as JTAG boundaryscan and scanpath testing.

Conversion to the ATU18 series of ULC provides a significant reduction of the operat- ing power when compared to the original PLD or FPGA. The ATU18 series has a very low standby consumption, less than 0.145 nA/gate typically at commercial tempera-ture. Operating consumption is a strict function of clock frequency, which typically results in a significant power reduction depending on the device being compared. For a NAND2 cell the dynamic power consumption is 0.124uW/MHz at 1.8V.

ATU18 Maximum Ratings

Operating Temperature
Commercial................................................................0° to 70°C
Industrial................................................................-40° to 85°C
Military..................................................................-55° to 125°C
Max Supply Core Voltage (V_DD)........................................1.95 V
Max Supply Periphery Voltage (V_CC)....................................3.6V
3.3V Tolerant/Compliant...............................................Vcc +0.3V
Pad pullup resistor......................................................100Kohms
Pad pulldown resistor..................................................100Kohms
Output buffer drive range...........................................3 to 24 mA
leakage current at Temp=25C................................0.145nA/gate
NAND2 dynamic power consumption..........0.124uW/MHz at 1.8V
Storage Temperature.............................................-65° to 150°C

ATU18 Features

• High Performance ULC Family Suitable for Latest CPLDs and FPGAs conversion
• Very effective associated Physical synthesis/optimization Flow
• From 45K Gates up to 1000K Gates Supported
• From 55Kbit to 847Kbit DPRAM
• Compatible with Xilinx and Altera Latest FPGA's
• Pin-count: Over 700 pins
• VDD 1.8V +/- 0.15V for core; 1.8V, 2.5V, 3.3V for Periphery
• Any Pinout Matched
• Full Range of Packages: PQFP/TQFP/VQFP, BGA/FLBGA, PGA/PPGA, QFN, CS
• Available in Commercial, Industrial and Military Grades
• 0.18 um Drawn CMOS, 5 Metal Layers
• Library Optimised for best Synthesis, Place & route and Testability Generation (ATPG)
• High system clock Skew Control
• 250Mhz system clock, up to 400Mhz for local clock
• Power on Reset, PLL, Multiplier
• Standard 3, 6, 12, 24 mA I/Os
• LVCMOS, LVTTL, GTL, HSTL, LVPECL, PCI & LVDS Interfaces
• High Noise & EMC Immunity
• Thick Oxide periphery Allowing Interface with 2.5V and 3.3V Environments

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