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AV9171-07, AV917-10CS8, AV9172

Table of contents:
Info of AV9171-07
Info of AV917-10CS8
Info of AV9172

AV9171-07, AV917-10CS8, AV9172 Selling Leads, Datasheet

MFG:ICS Package Cooled:SOP16 D/C:03+

AV9171-07, AV917-10CS8, AV9172 Datasheet download

Five Points

Part Number: AV9171-07

MFG: ICS

Package Cooled: SOP16

D/C: 03+

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AV9172 General Description

The AV9172 is designed to generate low skew clocks for clock distribution in high-performance PCs and workstations. It uses phase-locked loop technology to align the phase and frequency of the output clocks with an input reference clock. Because the input to output skew is guaranteed to ±500ps, the part acts as a "zero delay" buffer.

The AV9172 has six configurable outputs. The AV9172-01 version has one output that runs at the same phase and frequency as the reference clock. A second output runs at the same frequency as the reference, but can either be in phase or 180° out of phase from the input clock. Two outputs are provided that are at twice the reference frequency and in phase with the reference clock. The final outputs can be programmed to be replicas of the 2x clocks or non-overlapping two phase clocks at twice the reference frequency. The AV9172-01 and AV9172-03 operates with input clocks from 10 MHz to 50 MHz while producing outputs from 10 MHz to 100 MHz. The AV9172-07 operates with input clocks from 20 to 100 MHz.

The use of a phase-locked loop (PLL) allows the output clocks to run at multiples of the input clock. This permits routing of a lower speed clock and local generation of a required high speed clock. Synchronization of the phase relationship between the input clock and the output clocks is accomplished when one output clock is connected to the input pin FBIN. The PLL circuitry matches rising edges of the input clock and output clocks.

AV9172 Maximum Ratings

VDD referenced to GND . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7V
Operating temperature under bias. . . . . . . . . . . . . . . . . 0°C to +70°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Voltage on I/O pins referenced to GND. . . . .. GND -0.5V to VDD +0.5V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

AV9172 Features

• AV9172-07 input is 66 MHz with 66 and 33 MHz output buffers
• AV9172-01 is pin compatible with Gazelle GA1210E
• ±250ps skew (max) between outputs
• ±500ps skew (max) between input and outputs
• Input frequency range from 10 MHz to 50 MHz
(-01, -03) and from 20 MHz to 100 MHz (-07)
• Output frequency range from 10 MHz to 100 MHz (-01, -03, -07)
• Special mode for two-phase clock generation
• Inputs and outputs are fully TTL-compatible
• CMOS process results in low power supply current
• High drive, 25mA outputs
• Low cost
• 16-pin SOIC (150-mil) or 16-pin PDIP package

AV9172 Connection Diagram

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