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AX88772ALF, AX88780, AX88782LF

Table of contents:
Info of AX88772ALF
Info of AX88780
Info of AX88782LF

AX88772ALF, AX88780, AX88782LF Selling Leads, Datasheet

MFG:ASIX Package Cooled:TQFP64 D/C:1012

AX88772ALF, AX88780, AX88782LF Datasheet download

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Part Number: AX88772ALF

MFG: ASIX

Package Cooled: TQFP64

D/C: 1012

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AX88780 General Description

The AX88780, single-chip non-PCI 16/32-bit 10/100M Fast Ethernet Controller, is a high performance and highly integrated local CPU bus Ethernet Controller with embedded 10/100Mbps PHY/Transceiver and 40KBytes SRAM. The AX88780 supports both 16-bit and 32-bit SRAM-like local CPU interfaces, providing a glue-less connection to most common embedded MCUs. The AX88780 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3/IEEE802.3u LAN standards. The AX88780 also provides an extra IEEE802.3u compliant media-independent interface (MII) to support other media type like the Home LAN PHY. The AX88780 also supports IP/TCP/UDP checksum in hardware to offload processing loading from microprocessor or microcontroller in an embedded system.

AX88780 Maximum Ratings

High-performance non-PCI local bus

16/32-bit SRAM-like host interface (US Patent Approval)
Supports big/little endian data bus type
Large embedded SRAM for packet buffers

32K bytes for receive buffer
8K bytes for transmit buffer

Supports IP/TCP/UDP checksum offloads
Supports interrupt with high or low active trigger mode

Single-chip Fast Ethernet controller

Compatible with IEEE802.3, 802.3u standards
Integrated Fast Ethernet MAC/PHY transceiver in one chip
Supports 10Mbps and 100Mbps data rate
Supports full and half duplex operations
Supports 10/100Mbps N-way Auto-negotiation operation
Supports IEEE 802.3x flow control for full-duplex operation
Supports back-pressure flow control for half-duplex operation
Supports packet length set by software
Supports optional MII interface for Ethernet PHY and HomePNA/HomePlug PHY applications

Supports Wake-on-LAN function by following events

Detection of a change in the network link state
Receipt of a Magic Packet

Supports optional EEPROM interface
Supports PCMCIA in 16-bit mode
Supports system reference clock from 40MHz to 100MHz
Supports LED pins for various network activity indications
Integrated voltage regulator and 25MHz crystal oscillator
3.3V power supply with 5V I/O tolerance
128-pin LQFP with CMOS process, RoHS package

AX88780 Connection Diagram

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