CD22103, CD22103A, CD22103AD735 Selling Leads, Datasheet
MFG:HAR Package Cooled:DIP D/C:310
CD22103, CD22103A, CD22103AD735 Datasheet download
Part Number: CD22103
MFG: HAR
Package Cooled: DIP
D/C: 310
CD22103, CD22103A, CD22103AD735
- Table of contents:
Info of CD22103
Info of CD22103A
Info of CD22103AD735
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About CD22103A
PDF/DataSheet Download
Datasheet: CD22103A
File Size: 48557 KB
Manufacturer: INTERSIL [Intersil Corporation]
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About CD22103A
PDF/DataSheet Download
Datasheet: CD22103A
File Size: 48557 KB
Manufacturer: INTERSIL [Intersil Corporation]
Download : Click here to Download
About CD2003GB
PDF/DataSheet Download
Datasheet: CD2003GB
File Size: 199565 KB
Manufacturer: 无锡华润华晶微电子有限公司
Download : Click here to Download
CD22103A General Description
The CD22103A is designed to code and decode HDB3 signals which are coded as binary digital signals (NRZ-lN) and (+HDB3 IN, -HDB3 IN), accompanied by sampling clocks (CTX) and (CRX). The two binary coded HDB3 outputs, (+HDB3 OUT, -HDB3 OUT) may be externally mixed to create the ternary HDB3 signals (See Figure 1).
The two binary HDB3 input signals have been split from the input ternary HDB3 in an external line receiver. The receiver decoder converts binary unipolar inputs (+HDB3 IN, -HDB3 IN), which were externally split from ternary bipolar HDB3 signals, and a synchronous clock signal (CRX) into binary unipolar NRZ signals (NRZ-OUT).
Received signals not consistent with HDB3 coding rules are detected as errors. The receiver error output (ERR) is active high during one CRX period of each bit of received data that is inconsistent with HDB3 coding rules.
An input string consisting of all ones (or marks) is detected and signaled by a high level at the Alarm Signal (AIS) output. The AIS output is set to a high level when less than three zeros are received during two consecutive periods of the Reset Alarm Inhibit Signal (RAIS). The AIS output is subsequently reset to a low level when three or more zeros are received during two periods of the reset signal (RAIS).
A diagnostic Loop-Test Mode may be entered by driving the Loop Test Enable Input (LTE) high. In this mode the HDB3 transmitter outputs (+HDB3 OUT, -HDB3 OUT) are internally connected to the HDB3 receiver inputs, and the external HDB3 receiver inputs, and the external HDB3 receiver inputs (+HDB3 IN, -HDB3 IN) are disabled. The NRZ binary output signal (NRZ - OUT) corresponds to the NRZ binary input signal (NRZ - IN) delayed by approximately 8 clock periods.
The Clock Receiver Output (CKR) is the product of the two HDB3 input signals or-ed together. The CRX clock signal may be derived from the CKR signal with external clock extraction circuitry. In the Loop Test Mode (LTE = 1) CKR is the product of the +HDB3 OUT and -HDB3 OUT signals or-ed together.
The CD22103A may also be used to perform the AMI to NRZ coding/decoding function. To use the CD22103A in this mode, the HDB3/AMI control input is driven low.
CD22103A Maximum Ratings
Supply Voltage (VDD)
(Voltages referenced to VSS Terminal) . . . . . . . . . . . . . -0.5 to 8V
Supply Voltage Range
For TA = Full Package Temperature Range . . . . . .. . . . 4.5V to 5.5V
Input Voltage (All Inputs) . . . . . . . . . . . . . . . . . . -0.5 to VDD +0.5V
Input Current (Any One Input) . . . . . . . . . . . . . . . .. . . . . . .±10mA
Power Dissipation
For TA = -40 to 60 (Package Type E). . . . . . . . . . . . . . .500mW
For TA = 60 to 85
(Package Type E) . . . . . . . .. . Derate Linearly 12mW/ to 200mW
For TA = -55 to 100 (Package Type D). . . . . . . . . . . . . .500mW
For TA = 100 to 125
(Package Type D) . . . . . . . . . . Derate Linearly 12mW/ to 200mW
Device Dissipation per Output Transistor
For TA = Full Package Temperature Range (All Types) . . . . . 100mW
(Voltages referenced to VSS Terminal) . . . . . . . . . . . . . -0.5 to 8V
Supply Voltage Range
For TA = Full Package Temperature Range . . . . . .. . . . 4.5V to 5.5V
Input Voltage (All Inputs) . . . . . . . . . . . . . . . . . . -0.5 to VDD +0.5V
Input Current (Any One Input) . . . . . . . . . . . . . . . .. . . . . . .±10mA
Power Dissipation
For TA = -40 to 60 (Package Type E). . . . . . . . . . . . . . .500mW
For TA = 60 to 85
(Package Type E) . . . . . . . .. . Derate Linearly 12mW/ to 200mW
For TA = -55 to 100 (Package Type D). . . . . . . . . . . . . .500mW
For TA = 100 to 125
(Package Type D) . . . . . . . . . . Derate Linearly 12mW/ to 200mW
Device Dissipation per Output Transistor
For TA = Full Package Temperature Range (All Types) . . . . . 100mW
CD22103A Features
• HDB3 Coding and Decoding for Data Rates from 50Kb/s to 10Mb/s in a Manner Consistent with CCITT G703 Recommendations
• HDB3/AMI Transmission Coding/Reception Decoding with Code Error Detection is Performed in Independent Coder and Decoder Sections
• All Transmitter and Receiver Inputs/Outputs are TTL Compatible
• Internal Loop Test Capability
• Pin and Functionally Compatible with Type MJ1471
• HDB3/AMI Transmission Coding/Reception Decoding with Code Error Detection is Performed in Independent Coder and Decoder Sections
• All Transmitter and Receiver Inputs/Outputs are TTL Compatible
• Internal Loop Test Capability
• Pin and Functionally Compatible with Type MJ1471
CD22103A Typical Application
The CD22103A is an LSI SOS integrated circuit which performs the HDB3 transmission coding and reception decoding functions with error detection. It is used in 2.048Mb/s and 8.448Mb/s transmission applications. The CD22103A performs HDB3 coding and decoding for data
rates from 50Kb/s to 10Mb/s in a manner consistent with CCITT G703 recommendations.
HDB3 transmission coding/reception decoding with code error detection is performed in independent coder and decoder sections. All transmitter and receiver inputs/outputs are TTL compatible.
The HDB3 transmitter coder codes an NRZ binary unipolar input signal (NRZ-IN) and a synchronous transmission clock (CTX) into two HDB3 binary unipolar RZ output signals (+HDB3 OUT, -HDB3 OUT). The TTL compatible output signals +HDB3 OUT, -HDB3 OUT are externally mixed to generate ternary bipolar HDB3 signals for driving transmission lines.
The receiver decoder converts binary unipolar inputs (+HDB3 IN, -HDB3 IN), which were externally split from ternary bipolar HDB3 signals, and a synchronous clock signal (CRX) into binary unipolar NRZ signals (NRZ-OUT).
The CD22103A operates with a 5V ±10% power supply voltage over the full military temperature range at data rates from 50Kb/s up to 10Mb/s.
rates from 50Kb/s to 10Mb/s in a manner consistent with CCITT G703 recommendations.
HDB3 transmission coding/reception decoding with code error detection is performed in independent coder and decoder sections. All transmitter and receiver inputs/outputs are TTL compatible.
The HDB3 transmitter coder codes an NRZ binary unipolar input signal (NRZ-IN) and a synchronous transmission clock (CTX) into two HDB3 binary unipolar RZ output signals (+HDB3 OUT, -HDB3 OUT). The TTL compatible output signals +HDB3 OUT, -HDB3 OUT are externally mixed to generate ternary bipolar HDB3 signals for driving transmission lines.
The receiver decoder converts binary unipolar inputs (+HDB3 IN, -HDB3 IN), which were externally split from ternary bipolar HDB3 signals, and a synchronous clock signal (CRX) into binary unipolar NRZ signals (NRZ-OUT).
The CD22103A operates with a 5V ±10% power supply voltage over the full military temperature range at data rates from 50Kb/s up to 10Mb/s.
CD22103A Connection Diagram
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