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CDC924DL, CDC924DLR, CDC925

Table of contents:
Info of CDC924DL
Info of CDC924DLR
Info of CDC925

CDC924DL, CDC924DLR, CDC925 Selling Leads, Datasheet

MFG:Texas Instruments Category:Integrated Circuits (ICs) Package Cooled:81FY3J D/C:SSOP/56

CDC924DL, CDC924DLR, CDC925 Datasheet download

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Part Number: CDC924DL

Category: Integrated Circuits (ICs)

MFG: Texas Instruments

Package Cooled: 81FY3J

D/C: SSOP/56

Description: IC 133-MHZ CLOCK SYNTH 56-SSOP

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CDC924DL Parameters

Technical/Catalog Information	CDC924DL
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Type	Clock Synthesizer
Voltage - Supply	2.375 V ~ 2.625 V, 3.135 V ~ 3.465 V
Number of Outputs	19
Input	CMOS
Output	CMOS
Frequency-Max	133MHz
Package / Case	56-SSOP
Packaging	Tube
Operating Temperature	0°C ~ 85°C
Drawing Number	296; 4040048; DL; 28, 48, 56
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	CDC924DL CDC924DL 296 6714 5 ND 29667145ND 296-6714-5

CDC924DLR Parameters

Technical/Catalog Information	CDC924DLR
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Type	Clock Synthesizer
Voltage - Supply	2.375 V ~ 2.625 V, 3.135 V ~ 3.465 V
Number of Outputs	24
Input	CMOS
Output	CMOS
Frequency-Max	133MHz
Package / Case	56-SSOP
Packaging	Tape & Reel (TR)
Operating Temperature	0°C ~ 85°C
Drawing Number	296; 4040048; DL; 28, 48, 56
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	CDC924DLR CDC924DLR

CDC925 General Description

The CDC925 is a clock synthesizer/driver that generates system clocks necessary to support Intel Pentium III systems on CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz, and REF clock signals. All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input instead of a crystal can be provided at the XIN input. Two phase-locked loops (PLLs) are used, one to generate the host frequencies and the other to generate the 48-MHz clock frequency. On-chip loop filters and internal feedback loops eliminate the need for external components.
The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100.
The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN terminal, the device operates normally, but when a logical low-level input is applied, the device powers down completely, with the outputs in a low-level output state. When a high-level is applied to the PCI_STOP or CPU_STOP, the outputs operate normally. With a low-level applied to the PCI_STOP or CPU_STOP terminals, the PCI or CPU and 3V66 outputs, respectively, are held in a low-level state.
The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding setting for SEL133/100 control input. The PCI bus frequency is fixed to 33MHz.

CDC925 Maximum Ratings

Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance state or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 * IOL
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

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