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CDC925DL, CDC950, CDC950DGG

Table of contents:
Info of CDC925DL
Info of CDC950
Info of CDC950DGG

CDC925DL, CDC950, CDC950DGG Selling Leads, Datasheet

MFG:Texas Instruments Category:Integrated Circuits (ICs) Package Cooled:SOP D/C:1

CDC925DL, CDC950, CDC950DGG Datasheet download

Five Points

Part Number: CDC925DL

Category: Integrated Circuits (ICs)

MFG: Texas Instruments

Package Cooled: SOP

D/C: 1

Description: IC DIFF CLOCK SYNTH/DRVR 48TSSOP

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CDC925DL Parameters

Technical/Catalog Information	CDC925DL
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Type	Clock Synthesizer
Voltage - Supply	2.375 V ~ 2.625 V, 3.135 V ~ 3.465 V
Number of Outputs	19
Input	CMOS
Output	CMOS
Frequency-Max	133MHz
Package / Case	56-SSOP
Packaging	Tube
Operating Temperature	0°C ~ 85°C
Drawing Number	296; 4040048; DL; 28, 48, 56
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	CDC925DL CDC925DL 296 6715 5 ND 29667155ND 296-6715-5

CDC925DL General Description

Differential Clock Synthesizer/Driver for PC Motherboards

CDC925DL Features

Generates Clocks for Next Generation Microprocessors
Uses a 14.318-MHz Crystal Input to Generate Multiple Output Frequencies
Includes Spread Spectrum Clocking (SSC), 0.6% Downspread for Reduced EMI With Theoretical EMI of 7 dB
Power Management Control Terminals
Low Output Skew and Jitter for Clock Distribution
Operates From a Single 3.3-V Supply
Generates the Following Clocks:
- 8 Host (Diff Pairs, 100/133 MHz)
- 1 CLK33 (3.3 V, 33.3 MHz)
- 1 REFCLK (3.3 V, 14.318 MHz)
- 2 3V48 (3.3 V, 180° Shifted Pairs, 48 MHz)
Packaged in a 48-Pin TSSOP Package

CDC925DL Typical Application

CDC950 Datasheet

CDC950 Parameters

CDC950 Features

Generates Clocks for Next Generation Microprocessors
Uses a 14.318-MHz Crystal Input to Generate Multiple Output Frequencies
Includes Spread Spectrum Clocking (SSC), 0.6% Downspread for Reduced EMI With Theoretical EMI of 7 dB
Power Management Control Terminals
Low Output Skew and Jitter for Clock Distribution
Operates From a Single 3.3-V Supply
Generates the Following Clocks:
- 8 Host (Diff Pairs, 100/133 MHz)
- 1 CLK33 (3.3 V, 33.3 MHz)
- 1 REFCLK (3.3 V, 14.318 MHz)
- 2 3V48 (3.3 V, 180° Shifted Pairs, 48 MHz)
Packaged in a 48-Pin TSSOP Package

CDC950 General Description

Differential Clock Synthesizer/Driver for PC Motherboards

CDC950 Maximum Ratings

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, V_O (see Note 1) . . . . . . . . . . . . . . .. . . .. . . . . .. . . . . . . . . . . 0.5 V to 7 V
Current into any output in the low state, I_O . . .. .. . . . . . . . . . . . . . . . . . . . . . . . 2 * rated I_OL
Input clamp current, I_IK (V_I< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
                                         (VO > VDD) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, _JA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
Maximum power dissipation at TA = 55°C (in still air) (see Note 3) . . . . . . . . . . . . . . 1070 mW
Operating free-air temperature range, T_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
            2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for the through-hole packages,which use a trace length of zero.
            3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002.

CDC950 Features

Generates Clocks for Next Generation Microprocessors
Uses a 14.318-MHz Crystal Input to Generate Multiple Output Frequencies
Includes Spread Spectrum Clocking (SSC), 0.6% Downspread for Reduced EMI With Theoretical EMI of 7 dB
Power Management Control Terminals
Low Output Skew and Jitter for Clock Distribution
Operates From a Single 3.3-V Supply
Generates the Following Clocks:
- 8 Host (Diff Pairs, 100/133 MHz)
- 1 CLK33 (3.3 V, 33.3 MHz)
- 1 REFCLK (3.3 V, 14.318 MHz)
- 2 3V48 (3.3 V, 180° Shifted Pairs, 48 MHz)
Packaged in a 48-Pin TSSOP Package

CDC950 Typical Application

CDC950 Datasheet

CDC950 Connection Diagram

CDC950DGG Parameters

Technical/Catalog Information	CDC950DGG
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Type	Clock Synthesizer
Voltage - Supply	3.135 V ~ 3.465 V
Number of Outputs	11
Input	Crystal or Other
Output	HSCL
Frequency-Max	133MHz
Package / Case	48-TSSOP
Packaging	Tube
Operating Temperature	0°C ~ 85°C
Drawing Number	296; 4040078; DGG; 48, 56, 64
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	CDC950DGG CDC950DGG 296 9435 5 ND 29694355ND 296-9435-5

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