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CDC960DLRG4, CDC9841, CDC9841DW

Table of contents:
Info of CDC960DLRG4
Info of CDC9841
Info of CDC9841DW

CDC960DLRG4, CDC9841, CDC9841DW Selling Leads, Datasheet

MFG:Texas Instruments Category:Integrated Circuits (ICs) Package Cooled:TI D/C:08+

CDC960DLRG4, CDC9841, CDC9841DW Datasheet download

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Part Number: CDC960DLRG4

Category: Integrated Circuits (ICs)

MFG: Texas Instruments

Package Cooled: TI

D/C: 08+

Description: IC CLOCK DRVR 200 MHZ 48-SSOP

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CDC960DLRG4 Parameters

Technical/Catalog Information	CDC960DLRG4
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Type	Clock Synthesizer
Voltage - Supply	3.135 V ~ 3.465 V
Number of Outputs	10
Input	LVTTL
Output	LVTTL
Frequency-Max	133MHz
Package / Case	48-SSOP
Packaging	Tape & Reel (TR)
Operating Temperature	0°C ~ 70°C
Drawing Number	296; 4040048; DL; 28, 48, 56
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	CDC960DLRG4 CDC960DLRG4

CDC9841 General Description

The CDC9841 is a high-performance clock synthesizer/driver that generates all required clock signals necessary for a high-performance PC motherboard. The four central processing unit (CPU) clock outputs (PCLKn) are programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 control inputs. The six peripheral-component-interconnect (PCI) clock outputs (BCLKn) are half the frequency of PCLKn and are delayed 1 ns to 4 ns from the rising edge of the CPU clock. In addition, the four fixed-frequency outputs provide a 24-MHz clock (CLK24), a 12-MHz clock (CLK12), and two buffered copies of the 14.318-MHz input reference (REF0, REF1).

The CDC9841 generates all output frequencies from a 14.31818-MHz crystal input. A reference clock can be provided at X1 instead of a crystal input.

Two phase-lock loops (PLLs) generate the CPU clock frequency and the 24-MHz clock frequency. On-chip loop filters and internal feedback eliminate the need for external components. The PCI and 12-MHz clock frequencies are derived from the base CPU and 24-MHz clock frequencies, respectively. The PLL circuit can
be bypassed in the TEST mode (i.e., SEL0 = SEL1 = H) to distribute a test clock provided at the X1 input. Because the CDC9841 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at the X1 input, as well as following any changes to the SELn inputs.

PCLKn and BCLKn provide low-skew/low-jitter clock signals for reliable clock operation. All outputs are 3 state and are enabled via OE.

CDC9841 Maximum Ratings

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .0.5 V to 4.6 V
Input voltage range, V_I(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .0.5 V to 4.6 V
Voltage range applied to any output in the high state or power-off state,
V_O (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to V_CC + 0.5 V
Current into any output in the low state, I_O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 2 ^x IOHmax
Input clamp current, I_IK (V_I< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
Maximum power dissipation at T_A= 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . .1.2 W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C

CDC9841 Features

Four CPU Clock Outputs With Programmable Frequency (50 MHz, 60 MHz, and 66 MHz)
Six Clock Outputs at Half-CPU Frequency for PCI
One 24-MHz Clock Output
One 12-MHz Clock Output
Two 14.318-MHz Reference Outputs
All Output Clock Frequencies Derived From a Single 14.31818-MHz Crystal Input
LVTTL-Compatible Inputs and Outputs
Internal Loop Filters for Phase-Lock Loops Eliminate the Need for External Components
Operates at 3.3 V_CC
Distributed V_CC and Ground Pins Reduce Switching Noise
Packaged in Plastic Small-Outline Package

CDC9841 Connection Diagram

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