CDC9842, CDC9842DW, CDC9843 Selling Leads, Datasheet
MFG:TI Package Cooled:SOP D/C:96
CDC9842, CDC9842DW, CDC9843 Datasheet download
Part Number: CDC9842
MFG: TI
Package Cooled: SOP
D/C: 96
CDC9842, CDC9842DW, CDC9843
- Table of contents:
Info of CDC9842
Info of CDC9842DW
Info of CDC9843
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About CDC9842
PDF/DataSheet Download
Datasheet: CDC9842
File Size: 104069 KB
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About CDC111
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Datasheet: CDC111
File Size: 99053 KB
Manufacturer: TI [Texas Instruments]
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About CDC9843
PDF/DataSheet Download
Datasheet: CDC9843
File Size: 127132 KB
Manufacturer: TI [Texas Instruments]
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CDC9842 General Description
The CDC9842 is a high-performance clock synthesizer/driver that generates the system clocks necessary to support PentiumE/82430X/82430VX and PentiumPro 82440FX chipsets. Four host-clock outputs (HCLKn) are programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 control inputs. Six PCI-clock outputs (PCLKn) are half the frequency of CPU clock outputs and are delayed 1 ns to 4 ns from the rising edge of the CPU clock. In addition, a universal serial bus (USB) clock output at 48 MHz (SBCLK) and three 14.318-MHz reference clock outputs (REF0, REF1, REF2) are provided.
All output frequencies are generated from a 14.318-MHZ crystal input. A reference clock can be provided at the X1 input instead of a crystal input.
Two phase-locked loops (PLLs) are used to generate the host clock frequency and the 48-MHz clock frequency. On-chip loop filters and internal feedback eliminate the need for external components. The PCI-clock frequency is derived directly from the host-clock frequency. The PLL circuit can be bypassed in the TEST mode (i.e., SEL0 = SEL1 = H) to distribute a test clock provided at the X1 input.
The host- and PCI-clock outputs provide low-skew/low-jitter clock signals for reliable clock operation. All outputs are 3 state and are enabled via OE.
Because the CDC9842 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at the X1 input, as well as following any changes to the OE or SELn inputs.
CDC9842 Maximum Ratings
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance state or power-off state,
VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .0.5 V to VCC + 0.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . .1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance state or power-off state,
VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .0.5 V to VCC + 0.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . .1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C
CDC9842 Features
Provides System Clock Solution for PentiumTM/82430X/82430VX and PentiumPro 82440FX Chipsets
Four Host-Clock Outputs With Programmable Frequency (50 MHz, 60 MHz and 66 MHz)
Six PCI Clock Outputs at Half-CPU Frequency
One 48-MHz Universal Serial Bus (USB) Clock Output
Three 14.318-MHz Reference Clock Outputs
All Output Clock Frequencies Derived From a Single 14.31818-MHz Crystal Input
LVTTL-Compatible Inputs and Outputs
Internal Loop Filters for Phase-Locked Loops Eliminate the Need for External Components
Operates at 3.3 VCC
Packaged in Plastic Small-Outline Package
Four Host-Clock Outputs With Programmable Frequency (50 MHz, 60 MHz and 66 MHz)
Six PCI Clock Outputs at Half-CPU Frequency
One 48-MHz Universal Serial Bus (USB) Clock Output
Three 14.318-MHz Reference Clock Outputs
All Output Clock Frequencies Derived From a Single 14.31818-MHz Crystal Input
LVTTL-Compatible Inputs and Outputs
Internal Loop Filters for Phase-Locked Loops Eliminate the Need for External Components
Operates at 3.3 VCC
Packaged in Plastic Small-Outline Package
CDC9842 Connection Diagram
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