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CDCU2A877ZQLR, CDCU2A877ZQLT, CDCU877

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Info of CDCU2A877ZQLR
Info of CDCU2A877ZQLT
Info of CDCU877

CDCU2A877ZQLR, CDCU2A877ZQLT, CDCU877 Selling Leads, Datasheet

MFG:Texas Instruments (VA) Category:Integrated Circuits (ICs) Package Cooled:BGA-52 D/C:08

CDCU2A877ZQLR, CDCU2A877ZQLT, CDCU877 Picture

CDCU2A877ZQLR, CDCU2A877ZQLT, CDCU877 Datasheet download

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Part Number: CDCU2A877ZQLR

Category: Integrated Circuits (ICs)

MFG: Texas Instruments (VA)

Package Cooled: BGA-52

D/C: 08

Description: IC PLL CLOCK DRIVER 1.8V 52-BGA

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CDCU2A877ZQLR Parameters

Technical/Catalog Information	CDCU2A877ZQLR
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Type	PLL Clock Driver
Voltage - Supply	1.7 V ~ 1.9 V
Number of Outputs	10
Input	SSTL-18
Output	SSTL-18
Frequency-Max	410MHz
Package / Case	52-BGA MICROSTAR JUNIOR
Packaging	Tape & Reel (TR)
Operating Temperature	0°C ~ 70°C
Drawing Number	296; 4204437-2/G; ZQL; 52
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	CDCU2A877ZQLR CDCU2A877ZQLR

CDCU2A877ZQLT Parameters

Technical/Catalog Information	CDCU2A877ZQLT
Vendor	Texas Instruments (VA)
Category	Integrated Circuits (ICs)
Type	PLL Clock Driver
Voltage - Supply	1.7 V ~ 1.9 V
Number of Outputs	10
Input	SSTL-18
Output	SSTL-18
Frequency-Max	410MHz
Package / Case	52-BGA MICROSTAR JUNIOR
Packaging	Cut Tape (CT)
Operating Temperature	0°C ~ 70°C
Drawing Number	296; 4204437-2/G; ZQL; 52
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	CDCU2A877ZQLT CDCU2A877ZQLT 296 20718 1 ND 296207181ND 296-20718-1

CDCU877 Parameters

CDCU877 Features

1.8V Phase Lock Loop Clock Driver for Double Data Rate ( DDR II ) Applications
Spread Spectrum Clock Compatible
Operating Frequency: 10 MHz to 400 MHz
Low Current Consumption: <135 mA
Low Jitter (Cycle-Cycle): ±30 ps
Low Output Skew: 35ps
Low Period Jitter: ±20 ps
Low Dynamic Phase Offset: ±15 ps
Low Static Phase Offset: ±50 ps
Distributes One Differential Clock Input to Ten Differential Outputs
52-ball µBGA (MicroStar Junior™ BGA, 0,65mm pitch) and 40-pin MLF
External Feedback Pins (FBIN, FBIN\) are Used to Synchronize the Outputs to the Input Clocks
Single-Ended Input and Single-Ended Output Modes
Meets or Exceeds JEDEC82-8 PLL Standard for PC2-3200/4200
Fail-Safe Inputs

CDCU877 General Description

1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications

CDCU877 Features

1.8V Phase Lock Loop Clock Driver for Double Data Rate ( DDR II ) Applications
Spread Spectrum Clock Compatible
Operating Frequency: 10 MHz to 400 MHz
Low Current Consumption: <135 mA
Low Jitter (Cycle-Cycle): ±30 ps
Low Output Skew: 35ps
Low Period Jitter: ±20 ps
Low Dynamic Phase Offset: ±15 ps
Low Static Phase Offset: ±50 ps
Distributes One Differential Clock Input to Ten Differential Outputs
52-ball µBGA (MicroStar Junior™ BGA, 0,65mm pitch) and 40-pin MLF
External Feedback Pins (FBIN, FBIN\) are Used to Synchronize the Outputs to the Input Clocks
Single-Ended Input and Single-Ended Output Modes
Meets or Exceeds JEDEC82-8 PLL Standard for PC2-3200/4200
Fail-Safe Inputs

CDCU877 Typical Application

CDCU877 Datasheet

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