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CDCV857, CDCV8578-1, CDCV857A

Table of contents:
Info of CDCV857
Info of CDCV8578-1
Info of CDCV857A

CDCV857, CDCV8578-1, CDCV857A Selling Leads, Datasheet

MFG:TI Package Cooled:TSSOP D/C:N/A

CDCV857, CDCV8578-1, CDCV857A Datasheet download

Five Points

Part Number: CDCV857

MFG: TI

Package Cooled: TSSOP

D/C: N/A

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CDCV857 Parameters

CDCV857 Features

Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 to 200 MHz
Low Jitter (cyc-cyc): ±75 ps
Distributes One Differential Clock Input to Ten Differential Outputs
Three-State Outputs When the Input Differential Clocks Are <20 MHz
Operates From Dual 2.5-V Supplies
48-Pin TSSOP Package
Consumes < 200-uA Quiescent Current
External Feedback PIN (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks

CDCV857 General Description

1:10 DDR Phase-Lock Loop Clock Driver

CDCV857 Features

Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 to 200 MHz
Low Jitter (cyc-cyc): ±75 ps
Distributes One Differential Clock Input to Ten Differential Outputs
Three-State Outputs When the Input Differential Clocks Are <20 MHz
Operates From Dual 2.5-V Supplies
48-Pin TSSOP Package
Consumes < 200-uA Quiescent Current
External Feedback PIN (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks

CDCV857 Typical Application

CDCV857 Datasheet

CDCV857A Parameters

CDCV857A Features

Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 to 180 MHz
Low Jitter (cyc-cyc): ±50 ps
Distributes One Differential Clock Input to Ten Differential Outputs
Three-State Outputs When the Input Differential Clocks Are <20 MHz
Operates From Dual 2.5-V Supplies
Available in a 48-Pin TSSOP Package or 56-Ball MicroStar Junior™ BGA Package
Consumes < 200-uA Quiescent Current
External Feedback PIN (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks

CDCV857A General Description

2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications

CDCV857A Maximum Ratings

Supply voltage range, V_DDQ, A_VDD . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V
Input voltage range, V_I(see Notes 1 and 2) . . . . . . . . . . . . .. 0.5 V to V_DDQ 0.5
Output voltage range, V_O (see Notes 1 and 2) . . . . . . . . . . 0.5 V to V_DDQ 0.5 V
Input clamp current, I_IK (V_I < 0 or V_I > V_DDQ) . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_DDQ) . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, I_O (V_O = 0 to V_DDQ) . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current to GND or V_DDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, _JA (see Note 3): DGG package . . . . . . .. . . 89°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137.6°C/W
Storage temperature range T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C

CDCV857A Features

Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 to 180 MHz
Low Jitter (cyc-cyc): ±50 ps
Distributes One Differential Clock Input to Ten Differential Outputs
Three-State Outputs When the Input Differential Clocks Are <20 MHz
Operates From Dual 2.5-V Supplies
Available in a 48-Pin TSSOP Package or 56-Ball MicroStar Junior™ BGA Package
Consumes < 200-uA Quiescent Current
External Feedback PIN (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks

CDCV857A Typical Application

CDCV857A Datasheet

CDCV857A Connection Diagram

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