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CDCV857ADGG, CDCV857ADGGR, CDCV857B

Table of contents:
Info of CDCV857ADGG
Info of CDCV857ADGGR
Info of CDCV857B

CDCV857ADGG, CDCV857ADGGR, CDCV857B Selling Leads, Datasheet

MFG:Texas Instruments (VA) Category:Integrated Circuits (ICs) Package Cooled:SSOP D/C:05+PB-FREE

CDCV857ADGG, CDCV857ADGGR, CDCV857B Datasheet download

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Part Number: CDCV857ADGG

Category: Integrated Circuits (ICs)

MFG: Texas Instruments (VA)

Package Cooled: SSOP

D/C: 05+PB-FREE

Description: IC SSTL-II PLL CLK-DRVR 48-TSSOP

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CDCV857ADGG Parameters

Technical/Catalog Information	CDCV857ADGG
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Type	PLL Clock Driver
Voltage - Supply	2.375 V ~ 2.625 V
Number of Outputs	10
Input	SSTL-2
Output	SSTL-2
Frequency-Max	200MHz
Package / Case	48-TSSOP
Packaging	Tube
Operating Temperature	0°C ~ 85°C
Drawing Number	296; 4040078; DGG; 48, 56, 64
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	CDCV857ADGG CDCV857ADGG 296 11575 5 ND 296115755ND 296-11575-5

CDCV857ADGG General Description

2.5 V Phase Lock Loop DDR Clock Driver

CDCV857ADGG Features

Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 MHz to 200 MHz
Low Jitter (cycle-cycle): ±50 ps
Low Static Phase Offset: ±50 ps
Low Jitter (Period): ±35 ps
Distributes One Differential Clock Input to 10 Differential Outputs
Enters Low-Power Mode When No CLK Input Signal Is Applied or PWRDWN Is Low
Operates From Dual 2.5-V Supplies
Available in a 48-Pin TSSOP Package or 56-Ball MicroStar Junior™ BGA Package
Consumes < 100-µA Quiescent Current
External Feedback Pins (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks
Meets/Exceeds the Latest DDR JEDEC Spec JESD82-1

CDCV857ADGG Typical Application

CDCV857B Datasheet

CDCV857ADGGR Parameters

Technical/Catalog Information	CDCV857ADGGR
Vendor	Texas Instruments (VA)
Category	Integrated Circuits (ICs)
Type	PLL Clock Driver
Voltage - Supply	2.375 V ~ 2.625 V
Number of Outputs	10
Input	SSTL-2
Output	SSTL-2
Frequency-Max	200MHz
Package / Case	48-TSSOP
Packaging	Digi-Reel?
Operating Temperature	0°C ~ 85°C
Drawing Number	296; 4040078; DGG; 48, 56, 64
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	CDCV857ADGGR CDCV857ADGGR 296 11575 6 ND 296115756ND 296-11575-6

CDCV857B Parameters

CDCV857B Features

Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 MHz to 200 MHz
Low Jitter (cycle-cycle): ±50 ps
Low Static Phase Offset: ±50 ps
Low Jitter (Period): ±35 ps
Distributes One Differential Clock Input to 10 Differential Outputs
Enters Low-Power Mode When No CLK Input Signal Is Applied or PWRDWN Is Low
Operates From Dual 2.5-V Supplies
Available in a 48-Pin TSSOP Package or 56-Ball MicroStar Junior™ BGA Package
Consumes < 100-µA Quiescent Current
External Feedback Pins (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks
Meets/Exceeds the Latest DDR JEDEC Spec JESD82-1

CDCV857B General Description

2.5 V Phase Lock Loop DDR Clock Driver

CDCV857B Features

Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 MHz to 200 MHz
Low Jitter (cycle-cycle): ±50 ps
Low Static Phase Offset: ±50 ps
Low Jitter (Period): ±35 ps
Distributes One Differential Clock Input to 10 Differential Outputs
Enters Low-Power Mode When No CLK Input Signal Is Applied or PWRDWN Is Low
Operates From Dual 2.5-V Supplies
Available in a 48-Pin TSSOP Package or 56-Ball MicroStar Junior™ BGA Package
Consumes < 100-µA Quiescent Current
External Feedback Pins (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks
Meets/Exceeds the Latest DDR JEDEC Spec JESD82-1

CDCV857B Typical Application

CDCV857B Datasheet

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