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DS3160, DS3160C01, DS31612

Table of contents:
Info of DS3160
Info of DS3160C01
Info of DS31612

DS3160, DS3160C01, DS31612 Selling Leads, Datasheet

MFG:DALLAS Package Cooled:LQFP-100P D/C:0127+

DS3160, DS3160C01, DS31612 Datasheet download

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Part Number: DS3160

MFG: DALLAS

Package Cooled: LQFP-100P

D/C: 0127+

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DS3160 General Description

The DS3160 device, which combines a line interface unit (LIU) with a formatter and framer, is compliant with the JT 6312kbps secondary-rate user-network interface and supports the G.704 and NTT J2 frame formats. A full-featured LIU with integrated jitter attenuator supports a software-programmable framer and formatter. Framer features include alarm and error detection, on-chip HDLC controller for processing of M-bit information, and programmable timeslot data-enable signal for 1.5Mbps, 3Mbps, 4.5Mbps, and 6Mbps frame formats. The formatter adds the required overhead to the user data and has the additional capability of generating diagnostic errors. Loopback features, together with an on-chip bit-error-rate test (BERT) function, allow easy isolation and monitoring of network segments.

DS3160 Maximum Ratings

Voltage Range on Any Pin with Respect to V_SS(Except V_DD) ...-0.3V to +5.5V
Supply Voltage (V_DD) Range with Respect to V_{SS ..................}-0.3V to +3.63V
Operating Temperature Range ...............................................0°C to +70°C
Storage Temperature Range............................................. -55°C to +125°C
Soldering Temperature .........................................See IPC/JEDEC J-STD-020A

*This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.

Note: The typical values listed below are not production tested.

DS3160 Features

· Single-chip JT 6312kbps secondary-rate line interface unit (LIU) and framer/formatter
· Supports G.704 and NTT J2 frame formats
· Transmit and receive path-monitor outputs
· B8ZS encoder and decoder
· Generates and detects alarms
· Integrated HDLC controller handles LAPD messages without host intervention
· Integrated BERT supports performance monitoring
· Supports 8-bit or 16-bit control
· 3.3V supply with 5V tolerant I/O; low-power CMOS
· Available in 100-pin LQFP package
· IEEE 1149.1 JTAG support

DS3160 Typical Application

· Routers
· Switches
· Test Equipment
· Aggregators/Concentrators
· PBX
· Base Stations

DS31612 General Description

The DS31612 (twelve), DS3168 (eight) and DS3166 (six) PHYs perform all of the functions necessary for mapping/de-mapping ATM cells and/or packets into as many as twelve DS3 Framed, E3 Framed or Clear-Channel data streams up to 52 Mbps. Each unit has independent receive and transmit paths. The receiver block performs data recovery from a B3ZS or HDB3-coded AMI signal and monitors for loss of the incoming signal and can be bypassed for direct clock and data inputs. The receiver block optionally performs B3ZS/HDB3 decoding. The transmit block performs B3ZS/HDB3 encoding and can be bypassed for direct clock and serial data outputs. Dedicated cell processor and packet processor blocks prepare outgoing cells or packets for transmission and check incoming cells or packets upon arrival. Built-in DS3/E3 framers transmit and receive cell/packet data in properly formatted (M23/C-bit) DS3, or (G.751/G.832) E3 data streams. PLCP framers provide legacy ATM transmission-convergence support. DSS scrambling is performed for clear-channel ATM cell support. With integrated hardware support for both cells and packets, the DS31612/8/6 PHYs enable high-density universal line cards for unchannelized DS3/E3/clear-channel from T3/E3/CC52 serial data to ATM/Packet (UTOPIA/POS-PHY Level2/3/SPI-3) system switch interface. Functions that are not used are powered down to reduce device power

DS31612 Maximum Ratings

Voltage Range on Any Input, Bidirectional or Open-Drain
Output Lead with Respect to VSS ..................-0.5V to +5.5V
Supply Voltage (VDDIO) Range with Respect to VSSIO for IO Ring.-0.3V to +3.63V
Supply Voltage (VDDINT) Range with Respect to
VSSINT for Core Logic.-0.1V to +1.98V
Ambient Operating Temperature Range...............-40 to +85
Junction Operating Temperature Range .........-40 to +125 (Note 1)
Storage Temperature Range....................-65 to +125
Soldering Temperature ..........See IPC/JEDEC J-STD-020 Specification
Note 1: The specified temperature range is the junction temperature -40 to +125.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability. Ambient Operating Temperature Range is assuming the device is mounted on a JEDEC standard test board in a convection cooled JEDEC test enclosure.
Note: The typical values listed below are not production tested.

DS31612 Features

` 6 (DS3166), 8 (DS3168), or 12 (DS31612) ATM/Packet PHYs for DS3, E3, or Clear-Channel Up to 52Mbps
` Each Port Independently Configurable
` Interfaces to LIUs or SONET/SDH Devices
` Universal PHYs Map ATM Cells and/or HDLC Packets into DS3 or E3 Data Streams
` 6-, 8-, and 12-Port, Pin-Compatible Devices
` UTOPIA L2 or L3 or POS-PHY™ L2 or L3 or SPI-3 Interface with 8-, 16-, or 32-Bit Bus Width at an Operating Frequency Up to 104MHz
` Ports Independently Configurable for Cell or Packet Traffic in POS-PHY/SPI-3 Bus Modes
` Direct, PLCP, DSS, and Clear-Channel Cell Mapping
` Direct and Clear-Channel Packet Mapping
` Ports Independently Configurable for DS3, E3 Full and Subrate, and Arbitrary Framing Protocols Up to 52Mbps
` Programmable (Internal) or External Subrate DS3/E3 Circuitry
` DS3/E3/PLCP Alarm Generation and Detection
` Built-in HDLC Controllers with 256-Byte FIFOs for DS3 PMDL, G.751 Sn Bit, and G.832 NR/GC Bytes, and PLCP NR/GC Bytes
` On-Chip Per-Port BERTs for PRBS and Repetitive Pattern Generation, Detection, and Analysis
` Large Performance-Monitoring Counters for Accumulation Intervals of at Least 1 Second
` High-Speed Flexible Overhead Insertion/Extraction Ports for DS3, E3, and PLCP Framers
` Loopbacks Include Line, Diagnostic, Framer,Payload, and System Interface
` Ports can be Disabled to Reduce Power
` Integrated Clock Rate Adapter can Generate the Required 44.736MHz for DS3, 34.368MHz for E3,and/or 51.84MHz for CC52 from a Single Reference
` Clock Rate Adapter Reference Clock Frequency can be 44.736, 34.368, 77.76, 51.84, or 19.44MHz
` 8/16-Bit Generic Microprocessor Interface
` Transparent Software Upgrade from Existing DS3161DS3164 SingleQuad Port ATM/Packet PHY Devices
` Low-Power 1.8V Core, 3.3V I/O Operation (5V Tolerant I/O)
` Small 27mm² (1mm pitch) TE-PBGA Packaging
` -40 to +85 Industrial Temperature Range
` IEEE 1149.1 JTAG Test Port

DS31612 Typical Application

·Access Concentrators
· Multi-Service Access Platforms
·ATM and Frame Relay Equipment
·Routers and Switches
·SONET/SDH MSPP
·Test Equipment

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