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DSP5630IPW66, DSP5630PV100, DSP56311

Table of contents:
Info of DSP5630IPW66
Info of DSP5630PV100
Info of DSP56311

DSP5630IPW66, DSP5630PV100, DSP56311 Selling Leads, Datasheet

MFG:MOTO Package Cooled:QFP D/C:05+

DSP5630IPW66, DSP5630PV100, DSP56311 Picture

DSP5630IPW66, DSP5630PV100, DSP56311 Datasheet download

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Part Number: DSP5630IPW66

MFG: MOTO

Package Cooled: QFP

D/C: 05+

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DSP56311 General Description

The DSP56311 is intended for applications requiring a large amount of on-chip memory, such as networking and wireless infrastructure applications. The EFCOP can accelerate general filtering applications, such as echo-cancellation
applications, correlation, and general-purpose convolution-based algorithms.

DSP56311 Maximum Ratings

Rating¹	Symbol	Value^{1, 2}	Unit
Supply Voltage	V_CC	0.1 to 2.0	V
Input/Output Supply Voltage	V_CCQH	0.3 to 4.0	V
All input voltages	V_IN	GND 0.3 to V_CCQH + 0.3	V
Current drain per pin excluding V_CC and GND	I	10	mA
Operating temperature range	T_J	40 to +100
Storage temperature	T_STG	55 to +150
Notes: 1. GND = 0 V, V_CC = 1.8 V ± 0.1 V, V_CCQH = 3.3 V ± 0.3 V, T_J = 40 to +100, CL = 50 pF 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 3. Power-up sequence: During power-up, and throughout the DSP56311 operation, VCCQH voltage must always be higher or equal to V_CC voltage.

DSP56311 Features

High-Performance DSP56300 Core
• 150 million instructions per second (MIPS) (270 MIPS using the EFCOP in filtering applications) with a 150 MHz clock at 1.8 V core and 3.3 V I/O
• Object code compatible with the DSP56000 core with highly parallel instruction set
• Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 ´ 24-bit parallel Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control
• Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes optimized for DSP applications (including immediate offsets), on-chip instruction cache controller, on-chip memory-expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
• Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and triggering from interrupt lines and all peripherals
• Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock and output clock with skew elimination
• Hardware debugging support including On-Chip Emulation (OnCEÔ) module, Joint Test Action Group (JTAG) Test Access Port (TAP)

Enhanced Filtering Coprocessor (EFCOP)
• On-chip 24 ´ 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core
• Operation at the same frequency as the core (up to 150 MHz)
• Support for a variety of filter modes, some of which are optimized for cellular base station applications:
- Real Finite Impulse Response (FIR) with real taps
- Complex FIR with complex taps
- Complex FIR generating pure real or pure imaginary outputs alternately
- A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16
- Direct form 1 (DFI) Infinite Impulse Response (IIR) filter
- Direct form 2 (DFII) IIR filter
- Four scaling factors (1, 4, 8, 16) for IIR output
- Adaptive FIR filter with true least mean square (LMS) coefficient updates
- Adaptive FIR filter with delayed LMS coefficient updates

On-Chip Peripherals
• Enhanced DSP56000-like 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater)
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are enabled

DSP56311 Typical Application

• Wireless and wireline infrastructure applications
• Multi-channel wireless local loop systems
• DSP resource boards
• High-speed modem banks
• Packet telephony

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