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SuperSOTTM -3 P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package.
FDN358P Maximum Ratings
Symbol
Parameter
Ratings
Units
VDSS
Drain-Source Voltage
-30
V
VGSS
Gate-Source Voltage
±20
V
ID
Drain Current - Continuous (Note 1a) - Pulsed
-1.5
A
-5
PD
Power Dissipation for Single Operation (Note 1a) (Note 1b)
0.5
W
0.46
TJ, Tstg
Operating and StorageJunctionTemperatureRange
-55 to +150
FDN358P Features
-1.5 A, -30 V, R DS(ON) = 0.125 @ VGS = -10 V R DS(ON) = 0.20 @ VGS= - 4.5 V.
High power version of industry SOT-23 package: identical pin out to SOT-23; 30% higher power handling capability. High density cell design for extremely low R DS(ON) Exceptional on-resistance and maximum DC current capability.