GP3S105, GP4020, GP4020AG Selling Leads, Datasheet
MFG:SHARP Package Cooled:SMD DIP D/C:08+
GP3S105, GP4020, GP4020AG Datasheet download
Part Number: GP3S105
MFG: SHARP
Package Cooled: SMD DIP
D/C: 08+
GP3S105, GP4020, GP4020AG
- Table of contents:
Info of GP3S105
Info of GP4020
Info of GP4020AG
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About GP30
PDF/DataSheet Download
Datasheet: GP30
File Size: 63283 KB
Manufacturer: GE [General Semiconductor]
Download : Click here to Download
About GP4020
PDF/DataSheet Download
Datasheet: GP4020
File Size: 212221 KB
Manufacturer: ZARLINK [Zarlink Semiconductor Inc]
Download : Click here to Download
About GP400DDM12
PDF/DataSheet Download
Datasheet: GP400DDM12
File Size: 132605 KB
Manufacturer: DYNEX [Dynex Semiconductor]
Download : Click here to Download
GP3S105 Parameters
- Single-chip GPS correlator with Firefly MF1 microcontroller core
- ARM7TDMI (Thumb) Microprocessor, with JTAG ICEBreaker Debug Interface
- Fully configurable external memory data-bus
- Navstar GPS C/A code spread-spectrum Correlator with 12 independent correlation channels
- One Pulse Per Second (1 PPS) UTC-Aligned Timing Output, with 25 ns resolution
- 3.3 V Operation
- Low Current Power-Down Mode
- System Clock Generator with Phase Locked Loop
- 32 kHz Real Time Clock
- Dual UART
- 3-wire BuILD Serial Input/Output (BSIO) Interface
- 8 General Purpose Input/Output (GPIO) Lines
- Boot ROM, allowing Software Upload via UART
- 8 k Bytes Internal SRAM
- Compatible with GP2015 RF Front End
GP3S105 General Description
GPS Receiver Baseband Processor
GP3S105 Features
- Single-chip GPS correlator with Firefly MF1 microcontroller core
- ARM7TDMI (Thumb) Microprocessor, with JTAG ICEBreaker Debug Interface
- Fully configurable external memory data-bus
- Navstar GPS C/A code spread-spectrum Correlator with 12 independent correlation channels
- One Pulse Per Second (1 PPS) UTC-Aligned Timing Output, with 25 ns resolution
- 3.3 V Operation
- Low Current Power-Down Mode
- System Clock Generator with Phase Locked Loop
- 32 kHz Real Time Clock
- Dual UART
- 3-wire BuILD Serial Input/Output (BSIO) Interface
- 8 General Purpose Input/Output (GPIO) Lines
- Boot ROM, allowing Software Upload via UART
- 8 k Bytes Internal SRAM
- Compatible with GP2015 RF Front End
GP3S105 Typical Application
GP4020 Datasheet
GP4020 Parameters
- Single-chip GPS correlator with Firefly MF1 microcontroller core
- ARM7TDMI (Thumb) Microprocessor, with JTAG ICEBreaker Debug Interface
- Fully configurable external memory data-bus
- Navstar GPS C/A code spread-spectrum Correlator with 12 independent correlation channels
- One Pulse Per Second (1 PPS) UTC-Aligned Timing Output, with 25 ns resolution
- 3.3 V Operation
- Low Current Power-Down Mode
- System Clock Generator with Phase Locked Loop
- 32 kHz Real Time Clock
- Dual UART
- 3-wire BuILD Serial Input/Output (BSIO) Interface
- 8 General Purpose Input/Output (GPIO) Lines
- Boot ROM, allowing Software Upload via UART
- 8 k Bytes Internal SRAM
- Compatible with GP2015 RF Front End
GP4020 General Description
GPS Receiver Baseband Processor
GP4020 Maximum Ratings
Supply voltage (VDD) from ground (GND) -0·5V to +5·0V
Bias for 5V inputs +7·0V max.
Input voltage (any input pin) GND-0·5V to VDD+0·5V
Output voltage (any output pin) GND-0·5V to VDD+0·5V
Storage temperature -55°C to +150°C
Static discharge (HBM)* 2kV
Bias for 5V inputs +7·0V max.
Input voltage (any input pin) GND-0·5V to VDD+0·5V
Output voltage (any output pin) GND-0·5V to VDD+0·5V
Storage temperature -55°C to +150°C
Static discharge (HBM)* 2kV
GP4020 Features
- Single-chip GPS correlator with Firefly MF1 microcontroller core
- ARM7TDMI (Thumb) Microprocessor, with JTAG ICEBreaker Debug Interface
- Fully configurable external memory data-bus
- Navstar GPS C/A code spread-spectrum Correlator with 12 independent correlation channels
- One Pulse Per Second (1 PPS) UTC-Aligned Timing Output, with 25 ns resolution
- 3.3 V Operation
- Low Current Power-Down Mode
- System Clock Generator with Phase Locked Loop
- 32 kHz Real Time Clock
- Dual UART
- 3-wire BuILD Serial Input/Output (BSIO) Interface
- 8 General Purpose Input/Output (GPIO) Lines
- Boot ROM, allowing Software Upload via UART
- 8 k Bytes Internal SRAM
- Compatible with GP2015 RF Front End
GP4020 Typical Application
GP4020 Datasheet
GP4020 Connection Diagram
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