OR2T15A-6, OR2T15A6BA256, OR2T15A-6BA256 Selling Leads, Datasheet
MFG:ORCA Package Cooled:QFP D/C:8
OR2T15A-6, OR2T15A6BA256, OR2T15A-6BA256 Datasheet download
Part Number: OR2T15A-6
MFG: ORCA
Package Cooled: QFP
D/C: 8
OR2T15A-6, OR2T15A6BA256, OR2T15A-6BA256
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Info of OR2T15A-6
Info of OR2T15A6BA256
Info of OR2T15A-6BA256
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About OR2T15A-6BC208
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Datasheet: OR2T15A-6BC208
File Size: 3223740 KB
Manufacturer: ETC [ETC]
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About OR22
PDF/DataSheet Download
Datasheet: OR22
File Size: 20258 KB
Manufacturer: AMSCO [austriamicrosystems AG]
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About OR22
PDF/DataSheet Download
Datasheet: OR22
File Size: 20258 KB
Manufacturer: AMSCO [austriamicrosystems AG]
Download : Click here to Download
OR2T15A-6 General Description
The ATM UTOPIA Slave Core from Modelware† implements, in modular VHDL, the ATM forum's UTOPIA Level 1 and Level 2 specifications.
The core interfaces to the application (e.g., ATM physical or adaptation layer) via a generic FIFO-like access interface and to the ATM layer via a UTOPIA Level 1 or Level 2 interface (Figure 1). The core uses internal FIFOs for cell buffering and timing transfer between the application and the ATM layer.
The core (using 18-bit internal FIFOs) operates at 50 MHz in an OR2T15A-6 or an OR3T55-7 ORCA FPGA.
OR2T15A-6 Features
`UTOPIA Level 1/Level 2 with parity generation/ checking. In Level 2, all multi-PHY modes are supported:
- 1 RxClav/1 TxClav
- Direct status
- Multiplexed status polling
`8-/16-bit bus width
`Programmable cell length
`25/33/50 MHz operation
`Meets all UTOPIA setup and clock-to-output specifications
`FIFO control/monitoring with the following options:
- Internal 128* 9/64 *17 ORCA® FIFOs (scalable)
`Flexible control inputs with options for the following:
- Internal/external hardwiring
- Access via a parallel or serial microprocessor interface
`Supports the ORCA Series 2 and Series 3 families of FPGAs
`VHDL* source code for easy design integration
`ORCA-specific optimization, tailor-made for high performance
`Ample design flexibility using built-in interface and function options
`Verified functionality and standards compliance
- 1 RxClav/1 TxClav
- Direct status
- Multiplexed status polling
`8-/16-bit bus width
`Programmable cell length
`25/33/50 MHz operation
`Meets all UTOPIA setup and clock-to-output specifications
`FIFO control/monitoring with the following options:
- Internal 128* 9/64 *17 ORCA® FIFOs (scalable)
`Flexible control inputs with options for the following:
- Internal/external hardwiring
- Access via a parallel or serial microprocessor interface
`Supports the ORCA Series 2 and Series 3 families of FPGAs
`VHDL* source code for easy design integration
`ORCA-specific optimization, tailor-made for high performance
`Ample design flexibility using built-in interface and function options
`Verified functionality and standards compliance
OR2T15A-6 Typical Application
·ORCA ATM Physical Layer CSC Application Note (AP97-050FPGA available from Lucent Technologies)
·ORCA OR2CxxA and OR2TxxA Series Field Programmable Gate Arrays Data Sheet (DS98-022), January 1998
·ORCA OR3CxxA and OR3TxxA Series Field Programmable Gate Arrays Data Sheet (DS98-163-1), August 1998
·Asynchronous Transfer Mode: ATM Architecture and Implementation, Martin et al., Prentice Hall 1996
·ORCA OR2CxxA and OR2TxxA Series Field Programmable Gate Arrays Data Sheet (DS98-022), January 1998
·ORCA OR3CxxA and OR3TxxA Series Field Programmable Gate Arrays Data Sheet (DS98-163-1), August 1998
·Asynchronous Transfer Mode: ATM Architecture and Implementation, Martin et al., Prentice Hall 1996
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