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PCK2010R, PCK2010RADL, PCK2010RDL

Table of contents:
Info of PCK2010R
Info of PCK2010RADL
Info of PCK2010RDL

PCK2010R, PCK2010RADL, PCK2010RDL Selling Leads, Datasheet

MFG:PHILIPS Package Cooled:SOP56 D/C:08+

PCK2010R, PCK2010RADL, PCK2010RDL Picture

PCK2010R, PCK2010RADL, PCK2010RDL Datasheet download

Five Points

Part Number: PCK2010R

MFG: PHILIPS

Package Cooled: SOP56

D/C: 08+

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PCK2010R General Description

The PCK2010R is a clock generator (frequency synthesizer) chip for a Pentium II and other similar processors.

The PCK2010R has four CPU clock outputs at 2.5 V, two CPUDIV2 clock outputs running at 1/2CPU clock frequency (66 MHz or 50 MHz depending on the state of SEL133/100) and four 3V66 clocks running at 66MHz. There are eight PCI clock outputs running at 33 MHz. One of the PCI clock outputs is free-running. Additionally, the part has three 2.5 V IOAPIC clock outputs at 16.67 MHz and two 3.3 V reference clock outputs at 14.318 MHz. All clock outputs meet Intel's drive strength, rise/fall time, jitter, accuracy, and skew requirements.

The part possesses dedicated power-down, CPUSTOP, and PCISTOP input pins for power management control. These inputs are synchronized on-chip and ensure glitch-free output transitions. When the CPUSTOP input is asserted, the CPU clock outputs and 3V66 clock outputs are driven LOW. When the PCISTOP input is asserted, the PCI clock outputs are driven LOW.

PCK2010R Maximum Ratings

SYMBOL	PARAMETER	CONDITION	LIMITS		UNIT
SYMBOL	PARAMETER	CONDITION	MIN	MAX
V_DD3	DC 3.3 V core supply voltage		0.5	+4.6	V
V_DDQ3	DC 3.3 V I/O supply voltage		0.5	+4.6	V
V_DDQ2	DC 2.5 V I/O supply voltage		0.5	+3.6	V
I_IK	DC input diode current	V_I< 0		50	mA
V_I	DC input voltage	Note 2	0.5	5.5	V
I_OK	DC output diode current	V_O > V_CC or V_O < 0		±50	mA
V_O	DC output voltage	Note 2	0.5	V_CC + 0.5	V
I_O	DC output source or sink current	V_O = 0 to V_CC		±50	mA
T_STG	Storage temperature range		65	+150	°C
P_TOT	Power dissipation per package plastic medium-shrink (SSOP)	For temperature range: 40 to +125°Cabove +55°C deratelinearlywith11.3mW/K		850	mW

NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

PCK2010R Features

• Mixed 2.5 V and 3.3 V operation
• Four CPU clocks at 2.5 V
• Eight PCI clocks at 3.3 V, one free-running (synchronous with CPU clocks)
• Four 3.3 V fixed clocks @ 66 MHz
• Two 2.5 V CPUDIV2 clocks @ 􀀀 CPU clock frequency
• Three 2.5 V IOAPIC clocks @ 16.67 MHz
• One 3.3 V 48 MHz USB clock
• Two 3.3 V reference clocks @ 14.318 MHz
• Reference 14.31818 MHz Xtal oscillator input
• 133 MHz or 100 MHz operation
• Power management control input pins
• CPU clock jitter 3 250 ps cycle-cycle
• CPU clock skew 3 175 ps pin-pin
• 0.0ns 1.5 ns CPU - 3V66 delay
• 1.5ns 3.5 ns 3V66 - PCI delay
• 1.5ns 4.0 ns CPU - IOAPIC delay
• 1.5ns 4.0 ns CPU - PCI delay
• Available in 56-pin SSOP package
• ±0.5% center spread spectrum capability via select pins
• 0.5% down spread spectrum capability via select pins

PCK2010R Connection Diagram

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