Features: • Mixed 2.5V and 3.3V operation
• Four CPU clocks at 2.5V
• Eight synchronous PCI clocks at 3.3V, one free-running
• Two 2.5V IOAPIC clocks @ 14.318 MHz
• Two 3.3V 48MHz USB clock outputs
• Three 3.3V reference clocks @ 14.318 MHz
• Reference 14.31818 MHz Xtal oscillator input
• 100 MHz or 66 MHz operation
• Part provides frequencies for Pentium Pro and entium IIE motherboards
• Power management control input pins
• 175 ps CPU clock jitter
• 175 ps skew on outputs
• 1.5 4 ns CPUPCI delay
• Power down if PWRDWN is held LOW
• Available in 48-pin SSOP package
• See PCK2000M for 28-pin mobile versionPinout
Specifications
|
SYMBOL |
PARAMETER |
CONDITION |
LIMITS
|
UNIT
|
|
MIN |
MAX |
|
VDD3 |
DC 3.3 V core supply voltage |
|
0.5 |
+4.6 |
V |
|
VDDQ3 |
DC 3.3 V I/O supply voltage |
|
0.5 |
+4.6 |
V |
|
VDDQ2 |
DC 2.5 V I/O supply voltage |
|
0.5 |
+3.6 |
V |
|
IIK |
DC input diode current |
VI < 0 |
|
-50 |
mA |
|
VI |
DC input voltage |
Note 2 |
0.5 |
+5.5 |
V |
|
IOK |
DC output diode current |
VO > VCC or VO < 0 |
|
±50 |
mA |
|
VO |
DC output voltage |
Note 2 |
-0.5 |
VCC + 0.5 |
V |
|
IO |
DC output source or sink current |
VO >= 0 to VCC |
- |
±50 |
mA |
|
TSTG |
Storage temperature range |
|
65 |
+150 |
°C |
|
Ptot |
Power dissipation per package
plastic medium-shrink SO (SSOP) |
For temperature range: 0 to +70°Cabove +55°C derate linearly with 11.3mW/K |
- |
850 |
mW |
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DescriptionThe PCK2000 is a clock synthesizer/driver chip for a Pentium Pro or ther similar processors.
The PCK2000 has four CPU clock outputs at 2.5V. There are eight CI clock outputs running at 33MHz. One of the PCI clock outputs is ree-running. Additionally, the part has two 3.3V USB clock outputs t 48MHz, two 2.5V IOAPIC clock outputs at 14.318MHz, and three .3V reference clock outputs at 14.318MHz. All clock outputs meet ntel's drive strength, rise/fall time, jitter, accuracy, and skew equirements.
The part possesses dedicated powerdown, CPUSTOP, and CISTOP input pins for power management control. These inputs of PCK2000 re synchronized on-chip and ensure glitch-free output transitions. hen the CPUSTOP input is asserted, the CPU clock outputs are riven LOW. When the PCISTOP input is asserted, the PCI clock utputs are driven LOW, except for free running PCICLK_F clock utput..
Finally, when the PWRDWN input pin is asserted, the internal eference oscillator and PLLs are shut down, and all outputs are riven LOW.
The PCK2000 is available in a 48pin SSOP package.
PCK2000 Data Sheet
