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PCK2510SA, PCK2510SL, PCK2510SLDH

Table of contents:
Info of PCK2510SA
Info of PCK2510SL
Info of PCK2510SLDH

PCK2510SA, PCK2510SL, PCK2510SLDH Selling Leads, Datasheet

MFG:PHILIPS Package Cooled:01+ D/C:2982

PCK2510SA, PCK2510SL, PCK2510SLDH Picture

PCK2510SA, PCK2510SL, PCK2510SLDH Datasheet download

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Part Number: PCK2510SA

MFG: PHILIPS

Package Cooled: 01+

D/C: 2982

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PCK2510SA General Description

The PCK2510SA is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The PCK2510SA operates at 3.3 V VCC and is input compatible with both 2.5 V and 3.3 V input voltage ranges. It also provides integrated series damping resistors that make it ideal
for driving point-to-point loads.

One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the PCK2510SA does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the PCK2510SA requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference. The PLL can be bypassed for test purposes by strapping AVCC to ground.

The PCK2510SA is characterized for operation from 0 °C to +70 °C.

PCK2510SA Maximum Ratings

SYMBOL	PARAMETER	CONDITION	LIMITS		UNIT
SYMBOL	PARAMETER	CONDITION	MIN	MAX	UNIT
AV_CC	Supply voltage range	Note 2		< V_CC + 0.7	V
V_CC	Supply voltage range		0.5	+4.6	V
I_IK	Input clamp current	Note 2		50	mA
V_I	Input voltage range	Note 3	0.5	6.5	V
V_O	Output voltage range	V_O > V_CC or V_O < 0	-	±50	mA
I_OK	Output clamp current	Notes 3, 4	-0.5	V_CC+ 0.5	V
I_O	DC output source or sink current	V_O= 0 to V_CC		±50	mA
T_STG	Storage temperature range		-65	+150	°C
P_tot	Power dissipation per package		-	700	mW

NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. This value is limited to 3.6 V maximum.
4. This value is limited to 4.6 V maximum.

PCK2510SA Features

• Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications
• JEDEC compliant operation-PLL remains locked when outputs are disabled.
• See PCK2510SL for low power version where PLL goes into standby when outputs are disabled.
• Spread Spectrum clock compatible
• Operating frequency 50 to 150 MHz
• (tphase error jitter) at 100 to133 MHz = ±50 ps
• Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps
• Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps
• Pin-to-pin skew < 200 ps
• Available in plastic 24-Pin TSSOP
• Distributes one clock input to one bank of ten outputs
• External Feedback (FBIN) terminal Is used to synchronize the outputs to the clock input
• On-Chip series damping resistors
• No external RC network required
• Operates at 3.3 V
• See page 7 for Characteristic curves.

PCK2510SA Connection Diagram

PCK2510SL General Description

The PCK2510SL is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The PCK2510SL operates at 3.3 V VCC and is input compatible with both 2.5 V and 3.3 V input voltage ranges. It also provides integrated series damping resistors that make it ideal for driving point-to-point loads.

One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the PCK2510SL does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the PCK2510SL requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference. The PLL can be bypassed for test purposes by strapping AVCC to ground.

The PCK2510SL is characterized for operation from 0 °C to +70 °C.

PCK2510SL Maximum Ratings

SYMBOL	PARAMETER	CONDITION	LIMITS		UNIT
SYMBOL	PARAMETER	CONDITION	MIN	MAX	UNIT
AV_CC	Supply voltage range	Note 2		< V_CC + 0.7	V
V_CC	Supply voltage range		0.5	+4.6	V
I_IK	Input clamp current	Note 2		50	mA
V_I	Input voltage range	Note 3	0.5	6.5	V
V_O	Output voltage range	V_O > V_CC or V_O < 0	-	±50	mA
I_OK	Output clamp current	Notes 3, 4	-0.5	V_CC+ 0.5	V
I_O	DC output source or sink current	V_O= 0 to V_CC		±50	mA
T_STG	Storage temperature range		-65	+150	°C
P_tot	Power dissipation per package		-	700	mW

PCK2510SL Features

• Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications
• When outputs are disabled, the PLL and feedback output are disabled, dropping AICC to 100 mA in stand-by mode when input clock signal is present.
• See PCK2510SA for JEDEC compliant option where PLL remains locked when outputs are disabled.
• Spread Spectrum clock compatible
• Operating frequency 50 to 150 MHz
• (tphase error jitter) at 100 to133 MHz = ±50 ps
• Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps
• Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps
• Pin-to-pin skew < 200 ps
• Available in plastic 24-Pin TSSOP
• Distributes one clock input to one bank of ten outputs
• External Feedback (FBIN) terminal Is used to synchronize the outputs to the clock input
• On-Chip series damping resistors
• No external RC network required
• Operates at 3.3 V
• See page 7 for Characteristic curves.

PCK2510SL Connection Diagram

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