PCK857, PCK857DGG, PCK857DGV Selling Leads, Datasheet
MFG:PHILIPS Package Cooled:TSOP48 D/C:08+
PCK857, PCK857DGG, PCK857DGV Datasheet download
Part Number: PCK857
MFG: PHILIPS
Package Cooled: TSOP48
D/C: 08+
PCK857, PCK857DGG, PCK857DGV
- Table of contents:
Info of PCK857
Info of PCK857DGG
Info of PCK857DGV
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About PCK857
PDF/DataSheet Download
Datasheet: PCK857
File Size: 64092 KB
Manufacturer: PHILIPS [Philips Semiconductors]
Download : Click here to Download
About PCK857DGG
PDF/DataSheet Download
Datasheet: PCK857DGG
File Size: 64092 KB
Manufacturer: PHILIPS [Philips Semiconductors]
Download : Click here to Download
About PCK111
PDF/DataSheet Download
Datasheet: PCK111
File Size: 67168 KB
Manufacturer: PHILIPS [Philips Semiconductors]
Download : Click here to Download
PCK857 General Description
Zero delay buffer to distribute an SSTL differential clock input pair to 10 SSTL_2 differential output pairs. Outputs are slope controlled. External feedback pin for synchronization of the outputs to the input. A CMOS style Enable/Disable pin is provided for low power disable.
PCK857 Features
• Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications
• 1-to-10 differential clock distribution
• Very low skew (< 100ps) and jitter (< 100ps)
• 3V AVCC and 2.5V Vddq
• SSTL_2 interface clock inputs and outputs
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Full DDR solution provided when used with SSTL16857 and CBT3857
• 1-to-10 differential clock distribution
• Very low skew (< 100ps) and jitter (< 100ps)
• 3V AVCC and 2.5V Vddq
• SSTL_2 interface clock inputs and outputs
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Full DDR solution provided when used with SSTL16857 and CBT3857
PCK857 Connection Diagram
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