PCKV857, PCKV857A, PCKV857ADCV Selling Leads, Datasheet
MFG:PHILIPS Package Cooled:TSOP48 D/C:08.09+
PCKV857, PCKV857A, PCKV857ADCV Datasheet download
Part Number: PCKV857
MFG: PHILIPS
Package Cooled: TSOP48
D/C: 08.09+
PCKV857, PCKV857A, PCKV857ADCV
- Table of contents:
Info of PCKV857
Info of PCKV857A
Info of PCKV857ADCV
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About PCKV857
PDF/DataSheet Download
Datasheet: PCKV857
File Size: 86712 KB
Manufacturer: PHILIPS [Philips Semiconductors]
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About PCKV857A
PDF/DataSheet Download
Datasheet: PCKV857A
File Size: 103677 KB
Manufacturer: PHILIPS [Philips Semiconductors]
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About PCK111
PDF/DataSheet Download
Datasheet: PCK111
File Size: 67168 KB
Manufacturer: PHILIPS [Philips Semiconductors]
Download : Click here to Download
PCKV857 General Description
The PCKV857 is a high-performance, low-skew, low-jitter zero delay buffer designed for 2.5 V VDD and 2.5 V AVDD operation and differential data input and output levels.
The PCKV857 is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock outputs (FBOUT, FBOUT) . The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to high impedance state (3-State), and the PLL is shut down (low power mode). The device also enters the low power mode when the input frequency falls below 20 MHz. An input frequency detection circuit will detect the low frequency condition and after applying a > 20 MHz input signal, the detection circuit turns on the PLL again and enables the outputs. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PCKV857 is also able to track spread spectrum clocking for reduced EMI.
The PCKV857 is characterized for operation from 0 to +70 °C.
PCKV857 Maximum Ratings
|
SYMBOL |
PARAMETER |
CONDITION |
LIMITS
|
UNIT
| |
|
MIN |
MAX | ||||
|
VDDQ |
Supply voltage range |
0.5 |
3.6 |
V | |
|
AVDD |
Supply voltage range |
0.5 |
3.6 |
V | |
|
VI |
Input voltage range |
see Notes 2 and 3 |
0.5 |
VDDQ + 0.5 |
V |
|
VO |
Output voltage range |
see Notes 2 and 3 |
-0.5 |
VDDQ + 0.5 |
V |
|
IIK |
Input clamp current |
VI < 0 or VI >VDDQ |
- |
±50 |
mA |
|
IOK |
Output clamp current |
VO < 0 or VO >VDDQ |
- |
±50 |
mA |
|
IO |
Continuous output current |
VO = 0 to VDDQ |
±50 |
mA | |
|
Continuous current to GND or VDDQ |
- |
±100 |
mA | ||
|
Ptot |
Storage temperature range |
-65 |
+150 |
°C | |
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. This value is limited to 3.6 V maximum.
PCKV857 Features
• ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114.
• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
• Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications as per JEDEC specifications
• 1-to-10 differential clock distribution
• Very low skew (< 100 ps) and jitter (< 100 ps)
• Operation from 2.2 V to 2.7 V AVDD and 2.3 V to 2.7 V VDD
• SSTL_2 interface clock inputs and outputs
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Full DDR solution provided when used with SSTL16877 or SSTV16857
• See PCKV856 for I2C capable clock driver
• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
• Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications as per JEDEC specifications
• 1-to-10 differential clock distribution
• Very low skew (< 100 ps) and jitter (< 100 ps)
• Operation from 2.2 V to 2.7 V AVDD and 2.3 V to 2.7 V VDD
• SSTL_2 interface clock inputs and outputs
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Full DDR solution provided when used with SSTL16877 or SSTV16857
• See PCKV856 for I2C capable clock driver
PCKV857 Connection Diagram
PCKV857A General Description
The PCKV857A is a high-performance, low-skew, low-jitter zero delay buffer designed for 2.5 V VDD and 2.5 V AVDD operation and differential data input and output levels.
The PCKV857A is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock outputs (FBOUT, FBOUT) . The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is HIGH, the outputs switch in phase and frequency with CLK. When PWRDWN is LOW, all outputs are disabled to HIGH impedance state (3-State), and the PLL is shut down (LOW power mode). The device also enters the LOW power mode when the input frequency falls below 20 MHz. An input frequency detection circuit will detect the LOW frequency condition and after applying a > 20 MHz input signal, the detection circuit turns on the PLL again and enables the outputs.
When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PCKV857A is also able to track spread spectrum clocking for reduced EMI.
The PCKV857A is characterized for operation from 0 to +70 °C.
PCKV857A Maximum Ratings
|
SYMBOL |
PARAMETER |
CONDITION |
LIMITS
|
UNIT
| |
|
MIN |
MAX | ||||
|
VDDQ |
Supply voltage range |
0.5 |
3.6 |
V | |
|
AVDD |
Supply voltage range |
0.5 |
3.6 |
V | |
|
VI |
Input voltage range |
see Notes 2 and 3 |
0.5 |
VDDQ + 0.5 |
V |
|
VO |
Output voltage range |
see Notes 2 and 3 |
-0.5 |
VDDQ + 0.5 |
V |
|
IIK |
Input clamp current |
VI < 0 or VI >VDDQ |
- |
±50 |
mA |
|
IOK |
Output clamp current |
VO < 0 or VO >VDDQ |
- |
±50 |
mA |
|
IO |
Continuous output current |
VO = 0 to VDDQ |
±50 |
mA | |
|
Continuous current to GND or VDDQ |
- |
±100 |
mA | ||
|
Ptot |
Storage temperature range |
-65 |
+150 |
°C | |
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. This value is limited to 3.6 V maximum.
PCKV857A Features
• ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114.
• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
• Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications as per JEDEC specifications
• 1-to-10 differential clock distribution
• Very low skew (< 100 ps) and jitter (< 100 ps)
• Operation from 2.2 V to 2.7 V AVDD and 2.3 V to 2.7 V VDD
• SSTL_2 interface clock inputs and outputs
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Full DDR solution provided when used with SSTL16877 or SSTV16857
• Designed for DDR 266, 300, and 333 DIMM applications
• Available in TSSOP-48 and TVSOP-48 packages
• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
• Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications as per JEDEC specifications
• 1-to-10 differential clock distribution
• Very low skew (< 100 ps) and jitter (< 100 ps)
• Operation from 2.2 V to 2.7 V AVDD and 2.3 V to 2.7 V VDD
• SSTL_2 interface clock inputs and outputs
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Full DDR solution provided when used with SSTL16877 or SSTV16857
• Designed for DDR 266, 300, and 333 DIMM applications
• Available in TSSOP-48 and TVSOP-48 packages
PCKV857A Connection Diagram
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