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PIC18F258, PIC18F2580, PIC18F258-04/SO

Table of contents:
Info of PIC18F258
Info of PIC18F2580
Info of PIC18F258-04/SO

PIC18F258, PIC18F2580, PIC18F258-04/SO Selling Leads, Datasheet

MFG:MIC Package Cooled:SOP D/C:745

PIC18F258, PIC18F2580, PIC18F258-04/SO Picture

PIC18F258, PIC18F2580, PIC18F258-04/SO Datasheet download

Five Points

Part Number: PIC18F258

MFG: MIC

Package Cooled: SOP

D/C: 745

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PIC18F258 General Description

Parameter Name	Value
Program Memory Type	Flash
Program Memory (KB)	32
CPU Speed (MIPS)	10
RAM Bytes	1,536
Data EEPROM (bytes)	256
Digital Communication Peripherals	1-A/E/USART, 1-MSSP(SPI/I2C)
Capture/Compare/PWM Peripherals	1 CCP
Timers	1 x 8-bit, 3 x 16-bit
ADC	5 ch, 10-bit
CAN	1 ECAN
Temperature Range (C)	-40 to 125
Operating Voltage Range (V)	2 to 5.5
Pin Count	28

Features

PIC18F258 Maximum Ratings

Ambient temperature under bias............................................-40°C to +125°C
Storage temperature ............................................................ -65°C to +150°C
Voltage on any pin with respect to VSS (except V_DD, MCLR and RA4) ....... -0.3V to (V_DD + 0.3V)
Voltage on VDD with respect to VSS ........................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ........................... 0V to +13.25V
Voltage on RA4 with respect to VSS................................................ 0V to +8.5V
Total power dissipation (Note 1) ...............................................................1.0W
Maximum current out of VSS pin .............................................................300 mA
Maximum current into VDD pin ................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) ........................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ..................................±20 mA
Maximum output current sunk by any I/O pin............................................25 mA
Maximum output current sourced by any I/O pin ......................................25 mA
Maximum current sunk by all ports (combined) .......................................200 mA
Maximum current sourced by all ports (combined) ...................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = V_DD x {I_DD I_OH} + {(V_DD V_OH) x I_OH} + (V_OL x I_OL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/VPP pin rather than pulling this pin directly to V_SS.

PIC18F258 Features

• High current sink/source 25 mA/25 mA
• Three external interrupt pins
• Timer0 module: 8-bit/16-bit timer/counter with 8-bit programmable prescaler
• Timer1 module: 16-bit timer/counter
• Timer2 module: 8-bit timer/counter with 8-bit period register (time base for PWM)
• Timer3 module: 16-bit timer/counter
• Secondary oscillator clock option Timer1/Timer3
• Capture/Compare/PWM (CCP) modules;CCP pins can be configured as:
- Capture input: 16-bit, max resolution 6.25 ns
- Compare: 16-bit, max resolution 100 ns (TCY)
- PWM output: PWM resolution is 1 to 10-bit Max. PWM freq. @:8-bit resolution = 156 kHz 10-bit resolution = 39 kHz
• Enhanced CCP module which has all the features of the standard CCP module, but also has the following features for advanced motor control:
- 1, 2 or 4 PWM outputs
- Selectable PWM polarity
- Programmable PWM dead time
• Master Synchronous Serial Port (MSSP) with two modes of operation:
- 3-wire SPI™ (Supports all 4 SPI modes)
- I2C™ Master and Slave mode
• Addressable USART module:
- Supports interrupt-on-address bit

PIC18F258 Connection Diagram

PIC18F2580 General Description

The contents of register 'f' are decremented. If 'd' is '0', the result is placed in W. If 'd' is '1', the result is placed back in register 'f' (default)
If the result is '0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction.
If 'a' is '0', the Access Bank is selected.
If 'a' is '1', the BSR is used to select the GPR bank (default).
If 'a' is '0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See
Section 25.2.3 "Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.

PIC18F2580 Maximum Ratings

Ambient temperature under bias............-40°C to +125°C
Storage temperature.............................-65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR).........-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2)....................0V to +13.25V
Voltage on RA4 with respect to VSS.........................0V to +8.5V
Total power dissipation (Note 1) ................................1.0W
Maximum current out of VSS pin............................300 mA
Maximum current into VDD pin......................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD).........±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)............±20 mA
Maximum output current sunk by any I/O pin.......................25 mA
Maximum output current sourced by any I/O pin................25 mA
Maximum current sunk by all ports .............................200 mA
Maximum current sourced by all ports.............................200 mA

PIC18F2580 Features

C compiler optimized architecture with optiona extended instruction set
100,000 erase/write cycle Enhanced Flash program memory typical
1,000,000 erase/write cycle Data EEPROM memory typical
Flash/Data EEPROM Retention: > 40 years
Self-programmable under software control
Priority levels for interrupts
8 x 8 Single Cycle Hardware Multiplier
Extended Watchdog Timer (WDT):
- Programmable period from 41 ms to 131s
Single-Supply 5V In-Circuit Serial Programming(TM) (ICSP(TM)) via two pins
In-Circuit Debug (ICD) via two pins
Wide operating voltage range: 2.0V to 5.5V

Message bit rates up to 1 Mbps
Conforms to CAN 2.0B ACTIVE Specification
Fully backward compatible with PIC18XXX8 CAN modules
Three modes of operation:
- Legacy, Enhanced Legacy, FIFO
Three dedicated transmit buffers with prioritization
Two dedicated receive buffers
Six programmable receive/transmit buffers
Three full 29-bit acceptance masks
16 full 29-bit acceptance filters w/ dynamic association
DeviceNet(TM) data byte filter support
Automatic remote frame handling
Advanced error management features

PIC18F2580 Typical Application

In many applications, the ability to detect a drop below,or rise above a particular threshold is desirable. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach would indicate a high-voltage detect from, for example,3.3V to 5V (the voltage on USB) and vice versa for a detach. This feature could save a design a few extra components and an attach signal (input pin).

For general battery applications, Figure 22-4 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage VA, the HLVD logic generates an interrupt at time TA.The interrupt could cause the execution of an ISR,which would allow the application to perform "house-keeping tasks" and perform a controlled shutdown before the device voltage exits the valid operating range at TB. The HLVD, thus, would give the applica-tion a time window, represented by the difference between TA and TB, to safely exit.

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