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PM48128, PM49FL002, PM49FL002T-33JC

Table of contents:
Info of PM48128
Info of PM49FL002
Info of PM49FL002T-33JC

PM48128, PM49FL002, PM49FL002T-33JC Selling Leads, Datasheet

MFG:OAK Package Cooled:QFP D/C:05+

PM48128, PM49FL002, PM49FL002T-33JC Picture

PM48128, PM49FL002, PM49FL002T-33JC Datasheet download

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Part Number: PM48128

MFG: OAK

Package Cooled: QFP

D/C: 05+

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PM49FL002 General Description

The Pm49FL002/004 are 2 Mbit/4 Mbit 3.3 Volt-only Flash Memories used as BIOS in PCs and Notebooks. These devices are designed to use a single low voltage, ranging from 3.0 Volt to 3.6 Volt, power supply to perform insystem or off-system read, erase and program operations. The 12.0 Volt VPP power supply are not required for the program and erase operations of devices. The devices conform to Intel® Low Pin Count (LPC) Interface specification revision 1.1 and also read-compatible with Intel 82802 Firmware Hub (FWH) for most PC and Notebook applications.

The Pm49FL002/004 support two configurable interfaces: In-system hardware interface which can automatic detect the FWH or LPC memory cycle for in-system read and write operations, and Address/Address Multiplexed (A/A Mux) interface for fast manufacturing on EPROM Programmers. These devices are designed to work with both Intel Family chipset and Non-Intel Family Chipset platforms, it will provide PC and Notebook manufacturers great flexibility and simplicity for design, procurement, and material inventory.

The memory array of Pm49FL002 is divided into uniform 4 Kbyte sectors, or uniform 16 Kbytes blocks (sector group - consists of four adjecent sectors). The memory array of Pm49FL004 is divided into uniform 4 Kbyte sectors, or uniform 64 Kbyte blocks (sector group - consists of sixteen adjecent sectors). The sector or block erase feature allows users to flexibly erase a memory area as small as 4 Kbyte or as large as 64 Kbyte by one single erase operation without affecting the data in others. The chip erase feature allows the whole memory to be erased in one single erase operation. The devices can be programmed on a byte-by-byte basis after performing the erase operation.

The program operation of Pm49FL002/004 is executed by issuing the program command code into command register. The internal control logic automatically handles the programming voltage ramp-up and timing. The erase operation of the devices is executed by issuing the sector, block, or chip erase command code into command register. The internal control logic automatically handles the erase voltage ramp-up and timing. The preprogramming on the array which has not been programmed is not required before an erase operation. The devices offer Data# Polling and Toggle Bit functions in FWH/LPC and A/A Mux modes, the progress or completion of program and erase operations can be detected by reading the Data# Polling on I/O7 or Toggle Bit on I/O6.

The Pm49FL002 has a 16 Kbyte top boot block which can be used to store user security data and code. The Pm49FL004 has a 64 Kbyte top boot block. The boot block can be write protected by a hardware method controlled by the TBL# pin or a register-based protection turned on/off by the Block Locking Registers (FWH mode only). The rest of blocks except boot block in the devices also can be write protected by WP# pin or Block Locking Registers (FWH mode only).

The Pm49FL002/004 are manufactured on PMC's advanced nonvolatile technology, P-FLASH™. The devices are offered in 32-pin VSOP and PLCC packages with optional environmental friendly lead-free package.

PM49FL002 Maximum Ratings

Temperature Under Bisa		-55°C to +125°C
Storage Temperature		-65°C to +150°C
Surface Mount Lead Soldering Temperature	Standard Package	240°C 3 Seconds
	Lead-free Package	260°C 3 Second
Input Voltage with Respect to Ground on All Pin⁽²⁾		-0.5V to V_CC +0.5V
All Output Voltage with Respect to Ground		-0.5V to V_CC +0.5V
V_CC⁽²⁾		-0.5V to +6.0V

Notes:
1. Stresses under those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. The functional operation of the device or any other conditions under those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods may affected device reliability.
2. Maximum DC voltage on input or I/O pins are +6.25 V. During voltage transitioning period, input or I/O pins may overshoot to V_CC + 2.0 V for a period of time up to 20 ns. Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitioning period, input or I/O pins may undershoot GND to -2.0 V for a period of time up to 20 ns.

PM49FL002 Features

• Single Power Supply Operation
- Low voltage range: 3.0 V - 3.6 V
• Standard Intel Firmware Hub/LPC Interface
- Read compatible to Intel® 82802 Firmware Hub devices
- Conforms to Intel LPC Interface Specification Revision 1.1
• Memory Configuration
- Pm49FL002: 256K x 8 (2 Mbit)
- Pm49FL004: 512K x 8 (4 Mbit)
• Cost Effective Sector/Block Architecture
- Pm49FL002: Sixty-four uniform 4 Kbyte sectors, or sixteen uniform 16 Kbyte blocks (sector group)
- Pm49FL004: One hundred and twenty-eight uniform 4 Kbyte sectors, or eight uniform 64 Kbyte blocks (sector group)
• Top Boot Block
- Pm49FL002: 16 Kbyte top Boot Block
- Pm49FL004: 64 Kbyte top Boot Block
• Automatic Erase and Program Operation
- Build-in automatic program verification for extended product endurance
- Typical 25 µs/byte programming time
- Typical 50 ms sector/block/chip erase time
• Two Configurable Interfaces
- In-System hardware interface: Auto detection of Firmware Hub (FWH) or Low Pin Count (LPC) memory cycle for in-system read and write operations
- Address/Address-Multiplexed (A/A Mux) interface for programming on EPROM Programmers during manufacturing
• Firmware HUB (FWH)/Low Pin Count (LPC) Mode
- 33 MHz synchronous operation with PCI bus
- 5-signal communication interface for insystem read and write operations
- Standard SDP Command Set
- Data# Polling and Toggle Bit features
- Register-based read and write protection for each block (FWH mode only)
- 4 ID pins for multiple Flash chips selection (FWH mode only)
- 5 GPI pins for General Purpose Input Register
- TBL# pin for hardware write protection to Boot Block
- WP# pin for hardware write protection to whole memory array except Boot Block
• Address/Address Multiplexed (A/A Mux) Mode
- 11-pin multiplexed address and 8-pin data I/O interface
- Supports fast programming on EPROM programmers
- Standard SDP Command Set
- Data# Polling and Toggle Bit features
• Lower Power Consumption
- Typical 2 mA active read current
- Typical 7 mA program/erase current
• High Product Endurance
- Guarantee 100,000 program/erase cycles per single sector (preliminary)
- Minimum 20 years data retention
• Compatible Pin-out and Packaging
- 32-pin (8 mm x 14 mm) VSOP
- 32-pin PLCC
- Optional lead-free (Pb-free) package
• Hardware Data Protection

PM49FL002 Connection Diagram

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