PM7340-PI-AP, PM7340-PI-BP, PM7341 Selling Leads, Datasheet
MFG:PMC Package Cooled:BGA D/C:N/A
PM7340-PI-AP, PM7340-PI-BP, PM7341 Datasheet download

Part Number: PM7340-PI-AP
MFG: PMC
Package Cooled: BGA
D/C: N/A
MFG:PMC Package Cooled:BGA D/C:N/A
PM7340-PI-AP, PM7340-PI-BP, PM7341 Datasheet download

MFG: PMC
Package Cooled: BGA
D/C: N/A
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Datasheet: PM701
File Size: 263426 KB
Manufacturer:
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PDF/DataSheet Download
Datasheet: PM701
File Size: 263426 KB
Manufacturer:
Download : Click here to Download
PDF/DataSheet Download
Datasheet: PM7341
File Size: 3370167 KB
Manufacturer: PMC [PMC-Sierra, Inc]
Download : Click here to Download
The PM7341 S/UNI-IMA-84 is a monolithic integrated circuit that implements the
Inverse Multiplexing for ATM (IMA 1.1) protocol with backward compatibility to
IMA 1.0 and the Transmission Convergence (TC) layer function. The S/UNIIMA-
84 has two line side interface modes that determine the total number of links
supported: the Scalable Bandwidth Interconnect (SBI) bus interface mode and
the Clock and Data interface mode. In SBI mode, the S/UNI-IMA-84 supports up
to 84 T1, 63 E1 and 3 DS3 (TC only) links where each link is dynamically
configurable to support either IMA 1.1, backward compatible IMA 1.0, ATM over
T1/E1 and up to three ATM over DS3 streams (using HEC delineation).
In the Clock and Data interface mode, the S/UNI-IMA-84 supports 32
independent T1, E1 or unchannelized links. Each link is dynamically configurable
to support either IMA 1.1, backward compatible IMA 1.0, or ATM HEC cell
delineation. ATM over Fractional T1/E1 is also supported. Unchannelized links
may be used to support applications such as G.SHDSL.
All links within an IMA group must be the same nominal rate, however the link
rates within a group can be different across groups.
The Scaleable Bandwidth Interconnect (SBI) high-density byte serial system
interface provides higher levels of integration and dense interconnect. The SBI
bus interconnects up to 84 T1s or 63 E1s asynchronously. The SBI allows transmit timing to be mastered by the PHY layer device connected to the SBI bus with the S/UNI-IMA-84 always behaving as a clock slave. In addition to framed T1s and E1s, the S/UNI-IMA-84 can transport framed DS3 links over the SBI
bus.
The S/UNI-IMA-84 also supports a clock and data interface mode where 32 2-pin serial clock and data interfaces are provided. Each clock and data interface can be configured to support either a T1 link, E1 link, or an unchannelized link. For IMA, all links within a group must be the same nominal rate, but IMA groups consisting of either E1 or T1 links may coexist within the S/UNI-IMA-84. Additionally, for cell delineation only, ATM over fractional T1/E1 is supported by allowing individual DS0 timeslots to be configured as active or inactive.
IMA is a protocol designed to combine the transport bandwidth of multiple links into a single logical link. The logical link is called a group. The S/UNI-IMA-84 can support up to 42 independent groups with each group capable of supporting 1 to 32 links. Any link that is not participating in an IMA group can utilize the cell
The PM7341 S/UNI-IMA-84 is a monolithic integrated circuit that implements the ATM Forum Inverse Multiplexing for ATM (IMA 1.1) protocol with backward compatibility to IMA 1.0 and the Transmission Convergence (TC) layer function. The S/UNI-IMA-84 has two line side interface modes that determine the total number of physical links supported: the Scalable Bandwidth Interconnect (SBI) bus interface mode and the Clock and Data interface mode.
In SBI mode, the S/UNI-IMA-84 supports up to 84 T1, 63 E1 or 3 DS3 (TC only) physical links where each link is dynamically configurable to support either IMA 1.1, backward compatible IMA 1.0, ATM over T1/E1 or up to three ATM over DS3 streams (using HEC delineation).
In Clock and Data mode, the S/UNI-IMA-84 supports 32 independent T1, E1 or unchannelized physical links. Each link is dynamically configurable to support either IMA 1.1, backward compatible IMA 1.0, or ATM HEC cell delineation. ATM over fractional T1/E1 is also supported. Unchannelized links may be used to support applications such as G.SHDSL.
