PM73122

The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator-32) is a onolithic single chip device that provides DS1, E1, E3, or DS3 line interface ccess to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM etwork. It arbitrates access to an external SRAM for storage of the onfiguration, the user data, and the statistics. The device provides a icroprocessor interface for configuration, management, and statistics gathering. MC-Sierra also offers a software device control package for the AAL1gator-32 evice.
• Compliant with the ATM Forum's Circuit Emulation Services (CES) pecification (AF-VTOA-0078), and the ITU-T I.363.1
• Supports Dynamic Bandwidth Circuit Emulation Services (DBCES). ompliant with the ATM Forum's DBCES specification (AF-VTOA-0085). upports idle channel detection via processor intervention, CAS signaling, or ata pattern detection. Provides idle channel indication on a per channel asis.
• Supports non-DBCES idle channel detection by activating a queue when any f its constituent time slots are active, and deactivating a queue when all of ts constituent time slots are inactive.
Provides AAL1 segmentation and reassembly of 16 individual E1 or T1 lines,  H-MVIP lines at 8 MHz, or 2 E3 or DS3 or STS-1 unstructured lines.
• Using the optional Scalable Bandwidth Interconnect (SBI) Interface, provides AL1 segmentation and reassembly of up to 32 T1, E1, or 2 DS3 links. In BI mode can map any SBI tributary to any of the 32 AAL1 links. Supports loating and locked tributaries as well as unframed, framed without CAS and ramed with CAS tributaries. CAS is only supported on Synchronous ributaries.
• Provides a standard UTOPIA level 2 Interface which optionally supports parity nd runs up to 52 MHz. Only Cell Level Handshaking is supported. In MPHY ode, can act like a single port or 4 port device. The following modes are upported:
• 8/16-bit Level 2, Multi-Phy Mode (MPHY)
• 8/16-bit Level 1, SPHY
• 8-bit Level 1, ATM Master

The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator-32) is a onolithic single chip device that provides DS1, E1, E3, or DS3 line interface ccess to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM etwork. PM73122 arbitrates access to an external SRAM for storage of the onfiguration, the user data, and the statistics. PM73122 provides a icroprocessor interface for configuration, management, and statistics gathering. MC-Sierra also offers a software device control package for the AAL1gator-32 evice.