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PM73487-PI BGA 1210 PMC 2004+ -, PM73488, PM73488-P1

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Info of PM73487-PI BGA 1210 PMC 2004+ -
Info of PM73488
Info of PM73488-P1

PM73487-PI BGA 1210 PMC 2004+ -, PM73488, PM73488-P1 Selling Leads, Datasheet

MFG:PMC Package Cooled:PMC D/C:00+

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PM73487-PI BGA 1210 PMC 2004+ -, PM73488, PM73488-P1 Datasheet download

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Part Number: PM73487-PI BGA 1210 PMC 2004+ -

MFG: PMC

Package Cooled: PMC

D/C: 00+

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PM73488 General Description

The PM73488 (QSE) is an advanced communications device that enables the implementation of high performance switching systems. The QSE is a 32 *32 cell based switch element, with a total sustainable bandwidth of 5 Gb/s. (The peak, or raw, bandwidth is much more than that: about 8 Gb/s). The QSE is designed to be used with other QSE's as part of a larger switch fabric. Various QSE combinations allow fabrics with theoretical peak capacities ranging from 5 Gb/s (one QSE) to 160 Gb/s. The QSE is not ATM specific; however, should the QSE be used for switching ATM cells, the QSE cell size is large enough to allow efficient direct mapping between QSE Cells and ATM cells.

Multistage QSE Fabrics (Delta-Reverse Delta configuration) have rich connectivity with multiple paths between each source/destination pair. A QSE fabric performs cut-through unicast switching and uses Randomization and Evil-Twin algorithms to fully utilize these multiple paths and avoid the build up of internal hot spots. Randomization, in combination with multiple routing paths allows graceful degradation of QSE Fabric performance if internal links fail. To detect failed links, the QSE maintains and checks liveness patterns on input and output ports in hardware, and automatically routes around ports if they die.

QSE data ports are 6 bits wide including a 4-bit wide 66 MHz data path, a one-bit wide start-of-cell indication, and a one-bit wide acknowledgment signal. Each port contains "Phase Aligners" to recover the clock for that port, thus removing the need to synchronize all data to a single global clock. When switching unicast traffic in a multistage fabric (one to three stages), the first nibble of the cell will come out of the last QSE stage before the last nibble of that cell enters the first stage. The cell thereby traverses the entire fabric in one cell time. If the cell sucessfully makes it to its destination, the ("egress") device accepting the cell from the last stage QSE has the opportunity to send a four bit "Ack Information Packet" back to source indicating what it did with this cell; at its simplest, the egress device can send back one pattern to indicate that the cell was accepted and another to indicate that the cell was dropped due to, say, buffer overflow. It is also possible that the cell was dropped inside the QSE fabric due to say a collision with another cell.

The QSE classifies lost cells as due to one of three causes (collision, all possible outputs dead, or parity errors) and will generate an "Ack Information Packet" back to the source to communicate this event. In each QSE, the 4 bit pattern in the information packet can be independently software configured for each of the three cases. Note that since each QSE can be separately programmed, the patterns can even be setup so that the source knows where the cell was dropped.

The information provided by the "Ack Information Packets" can be used by the device injecting cells into the first QSE stage to decide how to handle the cells; at its simplest, the device can resend cells that did not get through (a more sophisticated algorithm might also take into account where the cell was lost and the behavior of the evil twin algorithm to decide when to resend the cell; for example if the cell was dropped due to output congestion it might make sense to back off on cells to that output). For unicast traffic, part of switch bandwidth will be used to resend cells that did not make it through the first time around. This implies that sustained throughput is less than peak switching capacity.

The amount of bandwidth required for resending cells and the effect of resending on latency and "Cell Delay Variation (CDV)" has been extensively studied with analytical models of the fabric. These results have then been cross checked with results from simulating software models of the fabric. This data is crucial for designing fabrics that can efficiently support Sheet guaranteed "Quality of Service (QOS)" requirements. The recommended QSE fabric configurations for high quality switching takes these results into account; for example the 3 stage 160 Gb/s sustained throughput fabric has a peak capacity of 256 Gb/s (60% margin).

The QSE fabric is store-and-forward for multicast traffic. Cell replication is performed in an optimal tree based manner where replication is done as far downstream as possible and each QSE contains cell buffers to buffer multicast cells. A multipriority backpressure feedback is used to control the flow of multicast cells through the fabric.

PM73488 Maximum Ratings

Symbol	Parameter	Conditions	Min	Max	Unit
V_DD	Supply voltage	With respect to GND	-0.3	3.9	V
I_OUT	DC output current, per pin	All outputs	-12	12	mA
T_STG	Storage temperature		-65	125	°C
T_J	Junction operating temperature		-40	125	°C
t_R	Input rise time			10	ns
t_F	Input fall time			10	ns
	ESD tolerance			1	kV
	Latch-up current			80	mA

PM73488 Features

   Switching Algorithm
• Supports blocking resolution in the switch fabric.
• Guarantees a lower bound on switch performance using a patented randomization algorithm called Evil
   Twin Switching.
• Determines routes using specified bits in the header (self-routing switch fabric) for unicast traffic.
• Determines output groupings using a lookup table for multicast traffic.
• Allows output ports to be combined in groups of 1, 2, 4, 8, 16, or 32 for unicast traffic.
• Allows output ports to be combined in groups of 1, 2, or 4 for multicast traffic.
   Multicast Support
• Supports optimal tree-based multicast replication in the switch fabric.
• Supports 512 internal multicast groups, expandable to 256K with external SRAM.
• Provides 64 internal cell buffers for multicast cells.
   Diagnostic/Robustness Features
• Checks the header parity.
• Counts tagged cells.
• Checks for connectivity and stuck-at faults on all switch fabric interconnects.
   I/O Features
• Provides 32 switch fabric interfaces with integrated phase aligner clock recovery circuitry.
• Provides a Start-Of-Cell (SOC) output per four switch element interfaces.
• Provides an external 8-bit Synchronous SRAM (SSRAM) interface for multicast group expansion.
• Provides a demultiplexed address/data CPU interface.
• Provides an IEEE 1149.1 (JTAG) boundary scan test bus.
   Physical Characteristics
• 3.3 V supply voltage.
• 5 V tolerant inputs.
• 596-pin Enhanced Plastic Ball Grid Array (EPBGA) package.
• Operates from a single 66 MHz clock.

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