PPC405CR, PPC405CR-3KC200C, PPC405CR-3KC266C Selling Leads, Datasheet
MFG:IBM Package Cooled:04 D/C:5000
PPC405CR, PPC405CR-3KC200C, PPC405CR-3KC266C Datasheet download

Part Number: PPC405CR
MFG: IBM
Package Cooled: 04
D/C: 5000
MFG:IBM Package Cooled:04 D/C:5000
PPC405CR, PPC405CR-3KC200C, PPC405CR-3KC266C Datasheet download

MFG: IBM
Package Cooled: 04
D/C: 5000
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PDF/DataSheet Download
Datasheet: PPC405CR
File Size: 457244 KB
Manufacturer: Applied Micro Circuits Corporation
Download : Click here to Download
PDF/DataSheet Download
Datasheet: PPC405CR-3KC200C
File Size: 457244 KB
Manufacturer: Applied Micro Circuits Corporation
Download : Click here to Download
PDF/DataSheet Download
Datasheet: PPC405CR-3KC266C
File Size: 457244 KB
Manufacturer: Applied Micro Circuits Corporation
Download : Click here to Download
The PowerPC 405CR (PPC405CR) is a 32-bit RISC embedded controller. High performance, peripheral integration, and low cost make the device ideal for wired communications, network printers, and other computing applications.
This device is an easy upgrade for systems based on PowerPC 403xx embedded processors, while providing a base for custom chip designs.
The controller is powered by a PPC405 embedded core. This core tightly couples a 266 MHz CPU, MMU, instruction and data caches, and debug logic. Finetuning of the core reduces data transfer overhead, minimizes pipeline stalls, and improves performance.
The PPC405CR employs the IBM CoreConnect™ bus architecture. This architecture, as implemented on the PPC405CR, consists of a 64-bit, 133-MHz Processor Local Bus (PLB) and a 32-bit, 66-MHz On-Chip Peripheral Bus (OPB). High-performance peripherals attach to the PLB and less performance-critical peripherals attach to the OPB.
Technology: CMOS SA-12E 0.25 µm (0.18 µm Leff)
Package: 27mm, 316-ball enhanced plastic ball grid array (E-PBGA)
Power (estimated): Typical 0.8W, Maximum 2.0W at 200MHz.
| Characteristic | Symbol | Value | Unit |
| Supply Voltage (Internal Logic) | VDD | 0 to +2.7 | V |
| Supply Voltage (I/O Interface) | OVDD | 0 to +3.6 | V |
| PLL Supply Voltage | AVDD | 0 to +2.7 | V |
| Input Voltage (2.5V CMOS receivers) | VIN | -0.6 to VDD+0.6 | V |
| Input Voltage (3.3V LVTTL receivers) | VIN | -0.6 to OVDD+0.6 | V |
| Input Voltage (5.0V LVTTL receivers) | VIN | 0.6 to OVDD+2.4 | V |
| Storage Temperature Range | TSTG | -55 to +150 | °C |
| Case temperature under bias | TC | -40 to +120 | °C |
