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QL8X12A-2PL68C, QL8X12A-OPL68C, QL8X12B

Table of contents:
Info of QL8X12A-2PL68C
Info of QL8X12A-OPL68C
Info of QL8X12B

QL8X12A-2PL68C, QL8X12A-OPL68C, QL8X12B Selling Leads, Datasheet

MFG:QUICKLOGIC Package Cooled:PLCC-68 D/C:09+

QL8X12A-2PL68C, QL8X12A-OPL68C, QL8X12B Picture

QL8X12A-2PL68C, QL8X12A-OPL68C, QL8X12B Datasheet download

Five Points

Part Number: QL8X12A-2PL68C

MFG: QUICKLOGIC

Package Cooled: PLCC-68

D/C: 09+

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QL8X12B General Description

The pASIC 1 Family of very-high-speed CMOS user-programmable ASIC (pASIC) devices is based on the first FPGA technology to combine high speed, high density and low power in a single architecture. pASIC 1 devices range in density from 1,000 to 8,000 usable ASIC gates, equivalent to 2,000 to 14,000 usable programmable (PLD) gates.

All pASIC 1 devices are based on an array of highly flexible logic cells which have been optimized for efficient implementation of high-speed arithmetic, counter, data path, state machine, random and glue logic functions. Logic cells are configured and interconnected by rows and columns of routing metal and ViaLink metal-to-metal programmable-via interconnect elements.

ViaLink technology provides a nonvolatile, permanently programmed custom logic function capable of operating at counter speeds of over 150 MHz. Internal logic cell nominal worst case delays are under 2 ns and total input to output combinatorial logic delays are under 8 ns. This permits high-density programmable devices to be used with today's fastest microprocessors, while consuming a fraction of the power and board area of PAL/GAL, CPLD and discrete logic solutions.

Designs can be entered on PC or workstation platforms using either QuickLogic's QuickWorks toolkit or a variety of popular third-party design-entry, logic synthesis and simulation tools. The QuickWorks toolkit provides design entry (VHDL, Verilog and schematic), place and route, timing analysis, simulation and programming for all QuickLogic devices. The pASIC 1 architecture provides sufficient on-chip routing to allow fully automatic place and route of designs using up to 100% of the available logic cells.

QL8X12B Features

`Very High Speed ViaLinkÒ metal-to-metal, programmable-via antifuse technology ensures useful internal logic function speeds at over 100 MHz, and logic cell delays of under 2 ns.
`High Usable Density Up to 8,000 usable ASIC gates, equivalent to 14,000 usable programmable logic (PLD) gates.
`Low Power/ 3.3 Volt Supply Stand-by current typically 2 mA with 5.0 Volt supply and less than 1 mA with 3.3 Volt supply.
`Flexible FPGA Architecture The pASIC 1 logic cell supports efficient, high-speed arithmetic, counter, data path, state machine and random logic applications with up to 14-input wide gates.
`Low-Cost, Easy-to-Use Design Tools Designs entered and simulated using QuickLogic's QuickWorks toolkit or third-party
`CAE tools. Fast, fully automatic place and route on PC and workstation platforms.

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