QL82SD

The QuickSD device is designed to address the need for high-speed serial communications. It maintains the features of standard discrete SERDES devices, but integrates these features with customizable logic to allow for the highest degree of flexibility, performance, and integration at the lowest cost. The QuickSD device is designed to support both transmit and receive requirements in a single chip. The device can support multiple channels in a variety of modes (with or without clock recovery,) a variety of translation widths (1:1 to 1:10), as well as a range of frequencies. These capabilities make this device ideal in applications where the performance is critical and customization is required.

The QuickSD device targets three applications: on-board, board-to-board (via common backplane), and box-to-box (via common cable).

The QL82SD device in the QuickLogic QuickSD ESP (Embedded Standard Product) device family provides a completely integrated configurable Serializer/Deserializer interface solution combined with 536 K system gates of customizable logic. This device provides a means to receive and transmit high-speed serial data and implement any proprietary high-speed serial link.

The QL82SD device QL82SD is a high performance serializer/deserializer chip. It can be combined with FIFO buffer memory to build a complete serial link. The need for external FIFOs can be eliminated by configuring the available internal RAM as two 256 x 36 FIFOs.

The embedded SERDES core of QL82SD is a full duplex design with a serialization section for transmission and a deserialization section for reception. The transmitter and receiver can be configured for level conversion (1:1), signals that transmit a clock signal with the data (1:4, 1:7, 1:8), or applications that require clock recovery (1:10).

The embedded SERDES core of QL82SD has a system interface that emulates a synchronous FIFO for ease of use. FIFOs allow maximum sustained performance of 600 MB/s running a full duplex link. Their function is to handle the asynchronous interface between the bus data rate and the different serial data rates, and handle phase and frequency differences inherent in serial links. Internal FIFOs of 256 × 36 or 512 × 16 can be cascaded with external FIFOs to expand the buffering to the desired size.

The QL82SD is a versatile part that allows the system designer to create proprietary or standardized serial links by taking advantage of some, or all, of the embedded features. It has a number of useful features for system designers of proprietary links with additions of embedded computational units and customizable I/O.