RT9641C, RT9642A, RT9643 Selling Leads, Datasheet
Package Cooled:SOP16 D/C:04+
RT9641C, RT9642A, RT9643 Datasheet download
Part Number: RT9641C
MFG: --
Package Cooled: SOP16
D/C: 04+
RT9641C, RT9642A, RT9643
- Table of contents:
Info of RT9641C
Info of RT9642A
Info of RT9643
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About RT9001
PDF/DataSheet Download
Datasheet: RT9001
File Size: 172035 KB
Manufacturer: Richtek Technology Corporation
Download : Click here to Download
About RT9001
PDF/DataSheet Download
Datasheet: RT9001
File Size: 172035 KB
Manufacturer: Richtek Technology Corporation
Download : Click here to Download
About RT9001
PDF/DataSheet Download
Datasheet: RT9001
File Size: 172035 KB
Manufacturer: Richtek Technology Corporation
Download : Click here to Download
RT9641C General Description
The RT9641C, paired with either the RT9230 or RT9231 simplifies the implementation of ACPI-compliant designs in microprocessor and computer applications. The IC integrates two linear controllers and a low-current pass transistor, as well as the monitoring and control functions into a 16-pin SOIC package. One linear controller generates the 3.3VDUAL voltage plane from an ATX power supply's 5VSB output during sleep states (S3,S4/S5), powering the PCI slots through an external pass transistor, as instructed by the status of the 3.3VDUAL enable pin. An additional pass transistor is used to switch in the ATX 3.3V output for PCI operation during S0 and S1 (active) operating states. The second linear controller supplies the computer system's 2.5V/3.3V memory power through an external pass transistor in active states. During S3 state, an integrated pass transistor supplies the 2.5V/3.3V sleep-state power. A third controller powers up a 5VDUAL plane by switching in the ATX 5V output in active states, or the ATX 5VSB in sleep states.
The RT9641C's operating mode (active-state outputs or sleep-state outputs) is selectable through two control pins: S3 and S5 Further control of the logic governing activation of different power modes is offered through two enabling pins: EN3VDL and EN5VDL. In active states, the 3.3VDUAL linear regulator uses an external N-channel pass MOSFET to connect the output (VOUT1) directly to the 3.3V input supplied by an ATX (or equivalent) power supply, while incurring minimal losses. In sleep state, the 3.3VDUAL output is supplied from the ATX 5VSB through a NPN transistor, also external to the controller. Active state power delivery for the 2.5V/3.3V VMEM output is done through an external NPN or a NMOS transistor. In sleep states, conduction on this output is transferred to an internal pass transistor. The 5VDUAL output is powered through two external MOS transistors. In sleep states, a PMOS (or PNP) transistor conducts the current from the ATX 5VSB output, while in active states, current flow is transferred to a NMOS transistor connected to the ATX 5V output. Similar to the 3.3VDUAL output, the operation of the 5VDUAL output is dictated not only by the status of the S3 and S5 pins, but that of the EN5VDL pin as well.
The RT9641C's operating mode (active-state outputs or sleep-state outputs) is selectable through two control pins: S3 and S5 Further control of the logic governing activation of different power modes is offered through two enabling pins: EN3VDL and EN5VDL. In active states, the 3.3VDUAL linear regulator uses an external N-channel pass MOSFET to connect the output (VOUT1) directly to the 3.3V input supplied by an ATX (or equivalent) power supply, while incurring minimal losses. In sleep state, the 3.3VDUAL output is supplied from the ATX 5VSB through a NPN transistor, also external to the controller. Active state power delivery for the 2.5V/3.3V VMEM output is done through an external NPN or a NMOS transistor. In sleep states, conduction on this output is transferred to an internal pass transistor. The 5VDUAL output is powered through two external MOS transistors. In sleep states, a PMOS (or PNP) transistor conducts the current from the ATX 5VSB output, while in active states, current flow is transferred to a NMOS transistor connected to the ATX 5V output. Similar to the 3.3VDUAL output, the operation of the 5VDUAL output is dictated not only by the status of the S3 and S5 pins, but that of the EN5VDL pin as well.
RT9641C Connection Diagram
/uploadfile/ic-mfg/407/ccf8a3b6-2dc7-4a2a-a33e-4d2f3e93c810.GIF
RT9643 General Description
The RT9643 is a combo regulator which is compliant to ACPI specification for desktop/motherboard power management and system application. The part features one switch regulator for DDR memory VDDQ power; three linear regulators including 1.5Amp peak sourcing/sinking capability regulator for DDR VTT, a 1.2V ultra-low-dropout linear controller for chipset miscellaneous power, a 3.3VSB power with 1.25Amp peak current capability; and 2 dual power control including 5VDL, and 3.3VDL control for S3 and S5 system power. The part totally feature 5 sets power which are compliant to ACPI specification into a single small footprint package VQFN-24L 5x5.
The part is generally operated to conform to ACPI specification, in S3 state, there are only VDDQ and 3.3VSB regulators remain on while the VTT and ULDO regulators are off. In the transition from S3 to S0, an external SS capacitor is attached for linear regulators to control its slew rates respectively to avoid inrush current induced. Moreover, the PGOOD signal raises high in S0 stage while all 3 regulators go stable. In the stage of S5 (EN = 0), there only 3.3VSB LDO remain on, while the other regulators are powered down. The VDDQ PWM regulator is a voltage mode implementation with external compensation to provide high load transient response. The VTT is regulated to follow 1/2 of VDDQ and is capable of sourcing or sinking 1.5A peak currents.
The part is generally operated to conform to ACPI specification, in S3 state, there are only VDDQ and 3.3VSB regulators remain on while the VTT and ULDO regulators are off. In the transition from S3 to S0, an external SS capacitor is attached for linear regulators to control its slew rates respectively to avoid inrush current induced. Moreover, the PGOOD signal raises high in S0 stage while all 3 regulators go stable. In the stage of S5 (EN = 0), there only 3.3VSB LDO remain on, while the other regulators are powered down. The VDDQ PWM regulator is a voltage mode implementation with external compensation to provide high load transient response. The VTT is regulated to follow 1/2 of VDDQ and is capable of sourcing or sinking 1.5A peak currents.
RT9643 Connection Diagram
/uploadfile/ic-mfg/407/a7a15020-c885-440e-a799-bdd2f2b6d768.GIF
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