T7263 ML, T7264, T-7264A- - ML-DT Selling Leads, Datasheet
MFG:LUCENT Package Cooled:LUCENT D/C:N/A
T7263 ML, T7264, T-7264A- - ML-DT Datasheet download
Part Number: T7263 ML
MFG: LUCENT
Package Cooled: LUCENT
D/C: N/A
T7263 ML, T7264, T-7264A- - ML-DT
- Table of contents:
Info of T7263 ML
Info of T7264
Info of T-7264A- - ML-DT
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About T720
PDF/DataSheet Download
Datasheet: T720
File Size: 737893 KB
Manufacturer: POWEREX [Powerex Power Semiconductors]
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About T7264
PDF/DataSheet Download
Datasheet: T7264
File Size: 897646 KB
Manufacturer: AGERE [Agere Systems]
Download : Click here to Download
About T-7290
PDF/DataSheet Download
Datasheet: T-7290
File Size: 1404336 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
T7264 General Description
The Lucent Technologies Microelectronics Group 7264 U-Interface 2B1Q Transceiver integrated circuit rovides full-duplex, basic-rate (2B+D) integrated ervices digital network (ISDN) communications on a -wire digital subscriber loop at either the LT or NT nd conforms to the ANSI North American Standard 1.601-1992. The single +5 V CMOS device is packaged n a 44-pin plastic leaded chip carrier (PLCC).
T7264 Maximum Ratings
| Parameter |
Typ |
Min |
Max |
Unit |
| Storage Temperature |
55 |
125 |
°C | |
| Lead Temp (soldering or bonding) |
300 |
°C | ||
| Any Pin to GND |
0.5 |
6.5 |
V | |
| Power Dissipation (package limit) |
700 |
mW |
T7264 Features
` U-interface 2B1Q transceiver
- Range over 18 kft on 26 AWG
- ISDN basic-rate 2B+D
- Full-duplex, 2-wire operation
- 2B1Q four-level line code
- Conforms to ANSI North American StandardT1.601-1992
- Supports NT quiet mode and insertion loss testmode for maintenance
` K2 interface
- 2B+D data
- 512 kbits/s TDM interface
- Frame and superframe markers
- Embedded operations channel (eoc)
- U-interface M bits and crc results
- Device control and status
` Other
- Single +5 V (±5%) supply
- 40°C to +85°C
- 44-pin PLCC
` Power consumption
- Operating 275 mW typical
- Idle mode 30 mW typical
` Analog front end
- On-chip line driver for 2.5 V pulses
- On-chip balance network
- Sigma-delta A/D converter
- Internal 15.36 MHz crystal oscillator
- Supports 15.36 MHz external clock input
` Digital signal processor
- Digital timing recovery (pull range ±250 ppm)
- Echo cancellation (linear and nonlinear)
- Accommodates distortion from bridged taps
- Scrambling/descrambling
- crc calculations
- Selectable LT or NT operation
- Start-up sequencing with timers
- Activation/deactivation support
- Cold start in 3.5 seconds (typical)
- Warm start in 200 ms (typical)
- U-frame formatting and decoding
- Range over 18 kft on 26 AWG
- ISDN basic-rate 2B+D
- Full-duplex, 2-wire operation
- 2B1Q four-level line code
- Conforms to ANSI North American StandardT1.601-1992
- Supports NT quiet mode and insertion loss testmode for maintenance
` K2 interface
- 2B+D data
- 512 kbits/s TDM interface
- Frame and superframe markers
- Embedded operations channel (eoc)
- U-interface M bits and crc results
- Device control and status
` Other
- Single +5 V (±5%) supply
- 40°C to +85°C
- 44-pin PLCC
` Power consumption
- Operating 275 mW typical
- Idle mode 30 mW typical
` Analog front end
- On-chip line driver for 2.5 V pulses
- On-chip balance network
- Sigma-delta A/D converter
- Internal 15.36 MHz crystal oscillator
- Supports 15.36 MHz external clock input
` Digital signal processor
- Digital timing recovery (pull range ±250 ppm)
- Echo cancellation (linear and nonlinear)
- Accommodates distortion from bridged taps
- Scrambling/descrambling
- crc calculations
- Selectable LT or NT operation
- Start-up sequencing with timers
- Activation/deactivation support
- Cold start in 3.5 seconds (typical)
- Warm start in 200 ms (typical)
- U-frame formatting and decoding
T7264 Connection Diagram
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